Cost Effectiveness Guides Every Technology Implementation

When asked when the limit of planar bulk CMOS devices will be met, Tak Ning, IBM fellow, responded, "The limits are originally set by device physics, but we will reach a practical limit before that that has to do with acceptable cost. For example, right around the 22 nm node, band-to-band tunneling will become so severe that it will be unacceptable for some devices. One thing is for sure: Until device quality data has been generated, we do not know the cost of a new technology."

Ning was one of several speakers at Semiconductor International's latest virtual conference, the Electronics Manufacturing Summit, which addressed 15 chapters of the 2005 International Technology Roadmap for Semiconductors (ITRS). In this webcast, he was joined by Peter Zeitzoff of Sematech, Alan Allen of Intel and Jim Hutchby of the Semiconductor Research Corp. to discuss the Process Integration, Devices and Structures (PIDS) chapter of the roadmap. All were in agreement that, no matter how great a technology might appear in development, whether it makes it into production is dictated by cost effectiveness. "We know we can build finFET devices, but can we build them with 10 nm gate lengths at a cost effective level in 10 years? That is the question," Zeitzoff said.

The performance roadmap from now until the end of the roadmap (Fig. 1 ) for high-performance (HP), low-standby-power (LSTP) and low-operating-power (LOP) devices shows the clear trade-off between switching speed and leakage. HP devices have been able to maintain a 17% per year improvement in CV/I, but at the expense of fairly high leakage. For LSTP devices, the leakage specification must be met, which leads to a hit in performance.

1. High-performance devices target 17%/year performance improvement, but at the expense of high leakage current. Low-standby-power devices target ~10 pA/µm leakage, so performance is sacrificed. Low-power devices, such as those used in laptops, fall in between. (Source: 2005 ITRS)

Some of the more interesting discussions center around the timeline for necessary technologies, such as strained silicon, high-k dielectric/metal gates, double-gate structures and fully depleted silicon on insulator (SOI). With the exception of strained silicon, all these technologies have been delayed to at least 2008 for initial implementation. "In terms of the limits of classical planar bulk CMOS, we expect that to come in around 2012, with 14 nm gate lengths. Multiple gate will likely come in around that time," Zeitzoff said. Channel engineering to replace silicon with SiGe, germanium, a compound semiconductor, or nanostructures are also being explored.

Ning commented on the practicality of SOI devices going forward. "SOI becomes the platform because all these others, such as finFETs and double-gate structures, are really variations on SOI because you have oxide on both sides of your conducting layer," he said.

There are different ways of designing and operating multigate devices. Essentially, they fall into two classes: a so-called standard finFET, where the gate surrounds the channel on two sides (dual gate) or three sides (trigate), and all parts are electrically connected and operated simultaneously. In a second approach, two or more gates can be alternatively biased. "You may be giving up some drive current with this approach, but it depends on how you optimize it," Zeitzoff said. Ning explained that the traditional approach has advantages if built on SOI because it provides ideal sub-threshold slope and the transistors can be switched using a smaller voltage compared with other device structures.

With many companies implementing strained silicon for the first time, the question of strain variation and its effect on CD control arises. "Both systematic and random stress variation occurs. If it is systematic, we work with the tool suppliers to improve things locally," Ning said. He added that the scalability of strained silicon methods is an area of active research.

A second webcast session addressed the Interconnects chapter, with a presentation from Christopher Case of BOC Edwards . The end of roadmap forecasts a high-performance microprocessor with a level 1 interconnect, 14 intermediate levels of wiring, five global levels and up to four passive element levels. Case pointed out that a growing concern is metal 1 resistance variability. "Manufacturers can expect perhaps a 30% deviation from a nominal specification due to CD variation. This is 3× worse than in earlier technologies," he said.

2. The move to multi-core microprocessors is having a positive impact on interconnect design. Critical path length in the core is reduced, less global wiring is needed, and pitches should be more uniform. (Source: ITRS 2006 Design TWG)

Another compelling concept to come out of this roadmap is the convergence of logic and DRAM metal 1 pitch around 2010. "This could give rise to a common back end, which could reduce manufacturing cost," Case said.

To address the growing concern of cross-talk, potential solutions include introducing lower-k dielectrics, adopting hybrid architecture (such as air gap approach), and reducing the k value of copper capping layers. At 65 nm, the roadmap shows one device manufacturer has successfully integrated leading k<2.4 and k<2.2 materials at 45 nm. Case added that, while the porous versions of established CVD films are being developed for low-k, air gap approaches remain viable as well.

At least one manufacturing concern, the size effect associated with scaling copper interconnects, appears to be put to rest. Though the physical problem has not gone away, it is being addressed effectively by process optimization and the design community. Adjustments are being made in the critical lower level and intermediate level interconnect levels. Wire height (Fig. 3 ) as well as line width is adjusted to reduce local resistivity increases associated with grain boundary and surface scattering contributions.

3. The increased resistivity of copper at decreased linewidths can be alleviated somewhat by adjusting the height of the wire. (Source: Infineon)

During the PIDS webcast, Jim Hutchby provided further insight into the post-CMOS era. One approach is to use the ultimate CMOS, which hopefully will be available in the next 8-10 years, and then add performance boosters to that platform: for instance, adding two resonant tunneling devices (RTDs) to the source and drain of the transistors. "Such a combination might attain more functionality at a lower transistor count or might reduce the power dissipation for the same functionality," he said. "Then there are more esoteric approaches that involve state vectors different from electronic charge. For instance, spin state could be used. The ability to use spin of individual nuclei or to couple the spins of two nuclei to obtain functionality in the quantum realm might be possible, but I think all of us would agree such approaches are decades away from being applied." Aside from spin state, the ability to harness a strongly coupled electron state also looks promising.