Extendible Process Using UV-Enhanced Gate Dielectric

As the channel length of the MOSFET is reduced, the gate dielectric thickness must be reduced in order to maintain acceptable short-channel effects and maximize drain current. The fundamental limit to the scaling of thin SiO₂ is the large leakage current caused by direct tunneling.¹ An oxide/nitride composite layer has been employed to improve the performance and reliability.² However, when the equivalent oxide thickness (EOT) of the gate dielectrics is reduced below 20 Å for advanced technology nodes, alternative high-permittivity (k) dielectrics, such as Ta₂O₅ or ZrO₂, must be considered.
 
High-k dielectrics may be formed by various novel techniques.^3,4 Thermal annealing has been found to reduce electrical leakage across the film by removing vacancies or other defects in the metal oxides. A problem in high-k gate stack involves unintentional "low-k" material formed at the interface during growth or post-deposition processing. Thermal stability of the high-k dielectrics is also an important property, defining its use in conventional CMOS process flows in which high thermal budget cycles exist. Many studies have demonstrated the important role of post-deposition anneal by rapid thermal processing (RTP) techniques in determining the final properties of high-k dielectrics.^5-7

For most high-k, thin-gate dielectrics, the interface to silicon is the dominant factor in determining the overall electrical properties. Even in the ideal case of completely eliminating interfacial reaction, the structure still contains several dielectrics in series, where the lowest k layer will dominate the overall capacitance and set a limit on the minimum achievable EOT value. Numerous studies have been reported on the ultrathin dielectric formation techniques, with increasing attention paid to low thermal budget RTP processes. RTP in appropriate ambient has demonstrated merits and potential in serving as a good interface between high-k dielectrics and silicon.^5-8

Oxynitride films have been investigated as gate dielectrics because of their enhanced reliability, including higher breakdown fields, longer time-to-breakdown, improved gate leakage, and less hot carrier degradation relative to conventional oxides with comparable EOT.^9,10 Incorporating nitrogen into the gate dielectric has also been examined as a diffusion barrier to boron in dual-gate CMOS technologies.¹¹ Oxynitride dielectrics have been grown by a variety of methods. Ammonia, nitrous oxide, and nitric oxide have all been used as nitriding agents.^12-15

The single-layer oxynitride has been modified significantly for applications by a scheme of multiple-layer composite dielectrics.^16,17 Most notable examples are those proposed by Kwong et al.,¹⁶ as shown in Figure 1 . The multilayer composite dielectric is usually formed after a dry preclean process, which typically consists of three steps,^18,19 namely:

UV-ozone (100 Torr) + HF-methanol vapor (100 Torr) + UV-Cl₂ (10 Torr)

Kwong's composite dielectrics process generally comprises the following four steps:

• NO (RTP, 20 sec, 800°C, 100-500 Torr) — to thermally grow an oxynitride film;
• NH₃/SiH₄ (CVD, 20 sec, 800°C, 1.5 Torr) — to deposit a chemical vapor deposition (CVD) SiN_x film;
• NH₃ (RTP, 30 sec, 950°C, 500 Torr) — to thermally densify the CVD SiN_x film;
• N₂O (RTP, 30 sec, 900°C, 500 Torr) — to reoxidize the composite dielectrics.

1. A typical multilayer gate stack process16 is usually formed after a dry preclean process. The first deposition step is the most critical.

In the four-step gate stack process, the first step is the most critical. The aim of this step is to grow an oxynitride layer of very low EOT, with appropriate nitrogen content in order to facilitate nucleation of silicon nitride on the oxynitride layer. The surface roughness of a CVD silicon nitride film deposited on a silicon dioxide layer has been found to have an undesirably high root mean square (RMS) roughness of ∼10 Å, and even up to 20 Å, when the physical thickness of the nitride layer is ∼25 Å and below. Published research papers^20-22 have indicated that the coalescence of nitride nucleation islands does not take place until the physical thickness of the silicon nitride film exceeds ∼20 Å. As the growth of silicon nitride films on oxide layers appears to be dependent upon having sufficient nucleation sites, thinner nitride films have had unacceptable surface roughness leading to unacceptable gate dielectric characteristics. Some studies have shown that remote plasma oxidation may improve the ultrathin oxide interface.²³ Unfortunately, remote plasma oxidation requires special processing equipment and is complicated to use. Therefore, alternative approaches to create more nucleation sites and reduce surface roughness of the thin silicon nitride films are being sought.

In this paper, we show the formation of an oxynitride layer on silicon using a novel UV-enhancement technique. We have used this UV-enhanced oxynitridation as the first step in a four-step gate stack process. The composite oxynitride gate stack dielectrics layers formed on the silicon substrate using this method have substantially improved performance.

Multilayer dielectric structures

An RTCVD two-chamber system clustered with a dry clean module was used in this work. The chamber had a base pressure of <5 × 10^-8 Torr. Prior to the oxynitride formation, the silicon substrate surface was cleaned with UV-excited ozone to remove organic residues. A HF-methanol vapor treatment was then applied to remove any grown oxide. Finally, UV-excited chlorine was used to remove metallic contaminants. After this precleaning step, the silicon substrate was exposed to UV radiation in an ambient containing O₂ and N₂. UV radiation is emitted from an external xenon lamp with a broad wavelength (200-1100 nm) output. The photon energies from the xenon lamp are 6.2 to 1.1 eV.

Experimental matrix of the UV-enhanced oxynitridation was carried out at a power of 100 to 200 W, in an atmosphere consisting of 2% to 12% O₂ in N₂, for 30 to 90 seconds at 100 to 150°C and 80 to 120 Torr. This resulted in the formation of a thin oxynitride film. A film of silicon nitride was then deposited over the oxynitride layer using a CVD process at 750°C. Next, the substrate was annealed in an NH₃ ambient at 900°C and 450 Torr. Finally, the substrate was annealed in a N₂O atmosphere at 800°C and 450 Torr.

The effect of surface cleaning on oxynitride thickness is very strong in NO oxynitridation. The in situ precleaning using only HF vapor results in much thicker oxide than that using all dry clean steps. Atomic force microscopy has been used to study the effect of UV-Cl₂ pretreatment on surface roughness of the CVD SiN_x deposited on oxynitrides grown in NO ambient. UV-excited Cl₂ has been found to increase the density of nucleation sites on silicon substrate for CVD silicon nitride deposition. This novel process²⁴ has been demonstrated to dramatically reduce the RMS roughness for a CVD silicon nitride film with a thickness of 22.5 Å. Similarly, the effect of UV-excited O₂ and N₂ has been found to be significant, as shown in Figure 2 .

The oxynitride thickness is ∼6 Å based on an analysis of ellipsometric and electrical data of the final gate stack. The composite oxynitride gate stack dielectrics layers formed on the silicon substrate using this method have substantially improved performance, with EOT values as low as 14.2 Å. A capacitance voltage plot for the composite oxynitride gate stack is shown in Figure 3 .

3. Electrical data for the composite oxynitride gate stack.

Figure 4 plots the leakage current densities versus EOT for various dielectrics. The leakage current densities for the composite gate stack dielectrics consisting of the UV-enhanced oxynitrides are in the order of 0.1 A/cm². These data appear to extend the capability of the more conventional DLK 4-step process.¹⁶ For the 100 nm node, the gate dielectric EOT should be 13 Å thick, with leakage current density less than 1.0 A/cm².

4. The leakage current densities for the composite gate stack dielectrics, consisting of the UV-enhanced oxynitrides, are in the order of 0.1 A/cm2. These data appear to extend the capability of the more conventional DLK 4-step process.16

Potential applications

When the EOT of the composite gate stack is reduced below 20 Å, alternative high-k dielectrics such as Ta₂O₅ or ZrO₂ must be considered. Earlier studies^5-7,19,25,26 of Ta₂O₅ have shown that this material is not thermally stable with silicon. Therefore, a thin barrier layer is required to prevent reaction and interdiffusion at the interface. Substrate preparation typically requires RTN in ammonia ambient prior to Ta₂O₅ deposition. The RTN-formed SiON layer, ∼12 Å thick, also serves to prevent the silicon surface from being oxidized during Ta₂O₅ CVD deposition, as well as slow down interfacial oxidation during post-deposition anneal of Ta₂O₅ in oxygen-containing ambient.²⁶ The SiON/Ta₂O₅ stacked gate dielectric exhibits three to five orders smaller leakage current than SiO₂ at 18 Å. The transistor characteristics are similar to those of SiO₂ transistor.^5-7 An n-channel MOSFET with EOT down to 18 Å has been demonstrated.

ZrO₂, HfO₂, and their silicates have been favored by various groups of researchers. MOS characteristics of ultrathin ZrO₂ dielectrics deposited on NH₃-treated silicon substrate at 475°C have been reported.²⁷ The boron penetration characteristics were compared using PMOS transistors with and without NH₃-annealed interface layer. RTA drive-in performed at 800 to 1000°C showed that the boron penetration could be suppressed by a thin nitride (<5 Å) interface. Further reduction of interfacial oxynitride thickness may be possible with the use of UV-enhanced process. This is important, as the 45 nm technology node demands a gate dielectric with EOT of 7 Å.

In collaboration with Kwong et al.,²⁸ we have fabricated MOS capacitors with ZrO₂/SiON gate stack on p-type (100) epitaxial silicon wafer for RTP anneal study. The electrode is TaN of 1800 to 2000 Å for the capacitors. The EOT for ZrO₂ film annealed in N₂ at 800°C for 60 seconds is 14 Å. A low leakage current of 50 mA/cm² at V_g=-1V is observed. ZrO₂ films with slightly thicker EOT of ∼18 Å exhibits leakage current density of approximately 10^-5 A/cm², nearly five orders of magnitude lower than that for SiO₂ films with the same thickness. Physical thickness of ZrO₂/SiON composite film has been determined by spectroscopic ellipsometry. By modeling these data, the thicknesses of interfacial oxynitride and the ZrO₂ film have been found to be about 5 and 40 Å, respectively. Using the EOT value determined by C-V measurements, the dielectric constant for ZrO₂ has been estimated as k=18.

Forming gas or wet H₂ appears to retard interfacial oxidation, indicating the importance of studying the effect of RTP anneal ambient on the quality of ZrO₂/Si interface. Further work is also needed to demonstrate the effect of interfacial morphology on the nucleation of ZrO₂ in a CVD process. A comparative study of thermal nitride and UV-enhanced oxynitride as interfacial barrier between ZrO₂ and silicon substrate would also be worthwhile.

Conclusions

We reported on the formation and characterization of some multilayer gate stacks. Emphasis has been made to correlate the interfacial barrier with the performance of the oxynitride and high-k dielectrics. The UV-enhanced oxynitride at the interface has demonstrated potential capability to improve leakage current density as the EOT continuously scales down in future technology nodes.

Acknowledgments

The authors wish to acknowledge Prof. D.L. Kwong and Mr. C.H. Lee for their contribution to the ZrO₂ work reported in this paper.

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