New Process Reduces Gate Leakage

Researchers at the University of Kentucky (Lexington) have shown that a comparatively simple rapid thermal processing (RTP) and anneal step could extend the life of conventional gate dielectrics, postponing the need to move to a high-k gate dielectric. As gate dielectrics get thinner, gate leakage is becoming more of a problem — so much so that some transistors consume almost as much power when they are off as when they are on. Reliability degradation is also a problem.

High-k materials provide a higher capacitance and higher effective oxide thickness, allowing charge to be more easily transferred from the gate to the source/drain region. Unfortunately, while some high-k materials have shown promise — most notably hafnium-based silicates — some severe integration problems still exist. These result in high threshold and flat-band voltage shifts, low mobility, and Fermi-level pining at the metal/gate oxide interface.

Zhi Chen, associate professor of electrical and computer engineering, found that RTP anneals in nitrogen and deuterium (D) can improve the insulating qualities of gate insulators so that their direct tunneling current is reduced by 10,000-100,000×. The RTP steps enhance a previously unknown phonon-energy-coupling effect (PECE), discovered by the researchers.

1. Schematic illustration of phonon-energy-coupling effect (PECE): Phonon energy from the Si-O rocking mode is coupled back to the Si-D bending mode and the Si-Si transverse optical phonon, leading to stronger Si-O bonds caused by rapid thermal processing (RTP) and deuterium (D) anneal of oxides.

The discovery of PECE came out of work that Chen and fellow researchers were doing based on an investigation of energy coupling between Si-D bonds and the Si-Si phonon mode (the phonon mode in solid materials is a vibration that consists of transverse optical and longitudinal optical (LO) components, as well as rocking and bending modes). They found that with the combination of the RTP and D anneal, strong coupling among the Si-D, Si-Si and Si-O bonds was observed. Both Si-D and Si-O bonds were strengthened dramatically when this effect was applied directly to the oxide (not to the polysilicon/oxide stack). This enhances the robustness of the oxide structure. The gate leakage current was reduced by five orders of magnitude for thin oxides (2.2 nm) and two orders of magnitude for thick oxides (>3 nm). The breakdown voltage was improved by ~30%.

In work presented in Applied Physics Letters, Chen and fellow researchers Jun Guo and Fuqian Yang suggest that the thermally induced PECE effect might be caused by the change of the oxide microstructure (stress and bond-angle change) caused by thermal effects. "The rapid cooling down (50°C/sec) likely preserves the microstructure change of the oxide, because we did not observe the PECE effect when the SiO₂ /Si sample was annealed in furnace for slow ramp-up (0.33°C/sec) and ramp-down (~0.1°C/sec)," they note. "We also observed that if the oxide is thicker than 800 Å, there is no PECE after the RTP. This suggests that the PECE may not exist for the polysilicon/oxide stack that might have larger tolerance for thermal shock. This also may explain why the semiconductor industry did not find this effect despite RTP being a routine process."

2. Gate leakage current density of silicon MOS capacitors with oxide thickness of 2.2 nm on n+ wafers (n=1 × 1019 cm-3) with D anneal only (450°C for 30 min) and RTP (1050°C in nitrogen for 1.0 min.) plus D anneal (450°C for 30 min). The leakage current reduction is equivalent to that of HfSiON.

Note from Editor: Regarding vibrational modes, see Brian C. Smith, Fundamentals of Fourier Transform Infrared Spectroscopy, CRC Press, 1996, and Molecular Vibration and Absorption.

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