Copper Now a Pillar of High-End Packaging
John Baliga, Contributing Editor -- Semiconductor International, 3/1/2006
It was recently revealed that Intel used copper pillar bumps for flip-chip attachment of its Yonah and Presler processors. Chipworks (Ottawa, Ontario, Canada) made the revelation, noting that they had never seen this attachment method used in production ICs before. This is a prominent example of a chip-scale packaging technique finding use in a higher-end 65 nm product.
In the chip-scale packaging explosion of the late 1990s, copper pillars were often used to increase the standoff height. Keeping the die farther away from the board or substrate surface makes it less sensitive to the strains caused by coefficient of thermal expansion (CTE) differences. This provided some of the advantages of using large solder balls for devices that were usually too small to have them. In some cases, the pillars were encased in the redistribution dielectric so that the dielectric could perform some of the functions of an underfill.
An important hallmark of chip-scale packaging technology is its efficiency. All the functions of a package have to be performed by a minimal amount of material. This efficiency was bound to become useful for larger packaging applications down the road, as more interconnections were being crammed into smaller spaces. Now we have commercial processors using what had been exclusively a chip-scale technology.
Copper pillar bumping can also make the use of lead-free solders more reliable. One of the reasons solder bumps have worked so well over the years is the ability of lead to absorb strains within the bump. This ability not only helped make the solder joints more reliable, it also helped to keep tin in the ball from experiencing too much strain. This is why tin whiskers were not as much of a concern as they are now. With the die far enough away from the substrate, strains in the solder joint can be smaller. The absence of lead poses less of a reliability problem than if the ball were providing all the mechanical support (Figure ).
This is likely to be one of many new approaches that will be used as pin counts and interconnection densities continue to increase.
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