E-Beam Inspection Aids Transistor Development

Chipmakers who are involved in edge-of-technology work are integrating numerous new materials and more exotic device architectures into volume production at the 65 nm node and below. Simultaneously, they are discovering that one unintended result of these efforts is that they now must deal with progressively subtler electrical problems and small physical defects across all device layers. In the case of memory, it can be poly-plug piping problems, where BPSG voids become an issue. In the logic area, it can be the use of strained silicon, where strained silicon dislocations can produce defects that sometimes do not become evident until very late stages of processing.

These defects' importance was unanticipated, and they either defy current detection methods or require longer inspection times for discovery. Although someone doing nickel silicide (NiSi) work on strained silicon, for example, may expect to find dislocation defects, he can also be unaware of exactly where these reside; he may be unable to locate the structure that they are specifically on or the orientation. All he knows is that these defects are abundantly present in early process development.

KLA-Tencor (San Jose) has introduced an e-beam inspection platform, the eS32, which has been designed for the capture of these yield-limiting buried electrical and small physical defects across all device layers at the 65 and 45 nm nodes. A basic advantage of any e-beam inspection system is that it tends to detect problems earlier. It will discover the dislocation defects, thus enabling the strained engineering to produce a faster device without having to pay a yield penalty, as well as accelerate the detection and resolution of systematic, yield-limiting defects in both FEOL and BEOL applications. Even when difficulties like those posed by NiSi and strained silicon are solved, later on in the processing these problems can reoccur, requiring monitoring of the line. The new platform provides the throughput needed for this, whether it is monitoring for copper BEOL voiding problems, open issues or subtle short issues.

Critical defect challenges in logic originate from changes in power and speed, leading to new classes of defect and noise. These are difficult to detect, because they are not simple opens, but can be design- and material-specific. (Source: KLA-Tencor)

DRAM manufacturers are faced with shorter product lifecycles and must ramp their new chips into high-volume production within increasingly shorter time spans. As they scale to smaller cells, critical FEOL and interconnect challenges can arise — from inspecting higher aspect ratio vias and capacitors to addressing the increasing yield impact of small physical defects. A critical new defect plaguing DRAMs is their production is subtle underetch on the poly plugs. Problem detection requires inspection through a highly resistive material: the unannealed poly. A low landing energy and a high extraction field, coupled with low beam current, increases the possibility of detection of these kinds of defects.

For logic manufacturers, a key concern is leakage — NiSi pipes and strained silicon dislocations. Unlike with a copper void where one looks for an open and connected versus unconnected metal (a problem relatively easy to find), this defect class is a subtle short requiring junction control. The platform can bias the junction and ground the short, a capability that enables it to look at dislocations and pipe defects.

These kinds of defects — dislocations and strained silicon, as well as piping issues — will occur in very specific structures. With dislocations, for instance, the stress of the local area where it was implanted and the number of curves all lead to a certain stress profile, which affects specific circuits.

To provide detection of these emerging defect types, the platform has capabilities in physical and voltage contrast sensitivity that enable faster time to root cause. The landing energy range has been extended to enhance capture of slight underetch contact defects. Also, beam current and scanning flexibility options have been designed for use on highly resistive materials, and to capture the growing array of subtle buried shorts. A smaller, 25 nm pixel has improved the capture of small physical defects in dense, high aspect ratio structures, and binning algorithms assist in the identification of systematic defect mechanisms.

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