The Wafer's Edge

In one of W. Somerset Maugham's celebrated novels, an Indian sage admonishes, "The pathway to salvation is as narrow and as difficult to walk as a razor's edge." Today, this pronouncement can be easily adapted to warn the process engineer, "The pathway to throughput is as fragile and as plagued with pitfalls as a wafer's edge."
 
As device architecture continues attaining finer linewidths, the wafer's edge cannot be disregarded. A prime mover behind this is the need to reduce progressively worse surface contamination that may migrate from a rough, pitted or fractured edge, and the necessity to avoid a catastrophic — contaminating — wafer explosion within the process chamber. Also, the realization that 5-7% of the wafer's surface area is missed if edge inspection is not done is transforming it into a technology enabler.

The edge is composed of three sections: the top bevel, the apex or crown, and the bottom bevel. Particularly over the last year, device manufacturers have looked closer at these sections and have included the edge exclusion. This is why inspection systems are evolving from looking at just the apex in a single pass of a single section, whether by laser or CCD, to the exclusion zone and around the edge — top bevel, apex, bottom bevel and backside edge exclusion — toward more inclusive wafer inspection.

For years, wafer surfaces — front and backsides — have been inspection's focus, with the edge not deemed crucial. Now it is important, because the wafer is manipulated from it and contacted in the carriers. "Contamination — not only particles, but metallic contaminants as well — in diffusion from the edge into the bulk and the near surface area is a critical issue," said Philip Blaustein, president of Hologenix (Huntington Beach, Calif.). "These atoms and metal particles tend to adhere to defects near the edge, so what starts as a scratch, a chip or a roughness induces metallic contamination."

Inspection focuses on edge polishing, CMP applications, layer inspection, flakes and contamination from one layer to another. This is especially true for 300 mm, where exclusion zones are shrinking. Edge contamination, whether metal or volatile particles transitioning from edge to surface — particularly with 65 nm linewidth — is important now, and a case can be made for edge inspection almost at every step. Backside vacuum used to be used to handle wafers, but since the 300 mm wafer is polished on both sides, nothing can contact its backside. Thus, they are handled by the edge, an area of concern that is being constantly tampered with.

John Valley, executive vice president at Raytex USA (Portland, Ore.), views CMP as an edge defectivity source. "The CMP process requires specific tuning to the edge condition," he said. "Edge conditions can vary from one wafer supplier to another, and even from one process tool to another. It's becoming something that must be measured and controlled."

Edge defects are plentiful because the edge is different from the front in cleanliness; also, polish quality is not as high. Depending on the shape of the edge, it can be difficult to maintain a specific smoothness level. This is why, if not applied at the silicon level, edge inspection becomes meaningless at the device level. It is important to eliminate 1 µm and submicron defects before the wafer reaches the device maker.

There is an ongoing competition between vision-based systems (CCD cameras or line-scan cameras) and laser-based systems to do edge inspection. Laser-based systems tend to be more sensitive to smaller defects. In terms of throughput, laser-based systems are faster, which is significant when having to inspect five sections on different planes; two edge exclusion zones top and bottom, the top and bottom bevels, and the apex. This includes the notch, because it is a transition point and can be just as damaging to active areas.

Most front-end-of-line (FEOL) inspection has developed considerably, but not much has happened at the edge because of process fluctuations, partial die, and color variations that make it difficult to inspect. According to Tuan Le, product manager for August Technology (Bloomington, Minn.), edge inspection began about eight years ago, with laser-based scanning tools, to find chips and cracks.

August's edge inspection approach is image-based, not a laser scanning process. Since the requirement is to deal with multiple surfaces, multiple cameras are used, a common technique updated by different lighting. Throughout edge normal, the wafer is examined at its apex. If the area is illuminated with a point light source, it is reflected and the camera sees a point of light. A different approach uses darkfield and diffused brightfield solutions. The darkfield focuses on the side, highlighting particulates. The diffuse brightfield source shows color variations, blister defects, delamination and low-aspect-ratio defects, as well as chips and cracks on the bevel.

Chip and crack detection is crucial because these cannot be hidden or reworked and, if mechanically or thermally stressed, can destroy the wafer. Another class of flaws is blisters. If there is a particulate — whether from resist, CMP or wafer carrier residues — and it is coated and run through a thermal process, a blister forms. This may not do damage at the next process step — it may be several layers later until it finally reaches a point at which it explodes.

Leading device makers require 100% edge inspection for blisters, chips and cracks. "One company has a formal yield management program," said Cory Watkins, August CTO. "They've studied edge defect types, excursions and process issues. They've mapped out the ROI on tightly controlling the bevel profile. SEMI's standards for bevel profile are still loose — there's a t/3, t/4, and then a full round bevel profile. This is too loosely toleranced. The analysis concluded that the smallest yield loss occurs when the entire edge is inspected. They're now also doing it at 200 mm, while others are specifying the actual bevel profile." Bevel profile influences yield loss, because layers do not adhere equally on a full round as they do on a t/3 or t/4. Additionally, depending on the grinding wheel's state when the profile was abraded on the wafer, there may be irregularities.

Current methodology for edge defectivity issues is manual edge inspection with an optical microscope. This should be automated, but device makers must first decide what they need — which areas to look at, at what sensitivity level, the best methods, how to carry out monitoring and, when defects are found, the corrective action.

There are some solutions. Applied Materials has an early-stage application for its SEM platforms, which uses an optical microscope to review the edge while capturing images (Fig.1 ). The system provides pictures that allow the monitoring to be customized, and attempts to locate macro edge defects to then navigate the SEM there. "As methodology matures and means are arrived at to avoid macro defects, attention will turn to smaller defects with demands for better inspection and review capabilities," said Renan Milo, defect review global product manager at Applied Materials' SEM Division in the Process Diagnostics and Control Group (Rehovoth, Israel).

1. By using automatic optical imaging when inspecting the wafer edge, it is possible to accurately navigate a SEM to the area of interest to do high-resolution review. (Source: Applied Materials)

Looking beneath

Surface optical techniques detect superficial defects. Typically, these methods may use laser beams focused at the wafer's edge, coming from up to four directions, and cameras. "Looking at the surface is insufficient," said Petra Feichtinger, product manager at Bede X-Ray Metrology (Durham, UK). "X-ray diffraction imaging directly maps distortions in the crystal lattice caused by defects such as buried cracks or surface scratches." The technique can identify these defects throughout the wafer and its edge, including both surfaces and the wafer bulk, and is insensitive to bevel shape variations.

X-ray diffraction detects even minute strain fields, such as at interfaces with oxide layers. However, X-ray diffraction's advantage is that, because it directly images the crystal lattice, inspection can be made on blanket and patterned wafers, a capability beyond optical imaging techniques. This enables defects introduced by wafer handling to be isolated and eliminated before they lead to device loss or wafer breakage, even up to a few metal layers.

OEMs like KLA-Tencor (San Jose) have platforms that target the topside and top bevel. "We have tools that can look at the wafer's top surfaces, but nothing currently that looks at the apex and lower bevel. Automated defect detection and classification in these regions is critical for IC manufacturing," said Frank Burkeen, director of marketing for growth and emerging markets. "A recent benchmark study of a dozen fabs discovered that the average yield loss on edge die is in the 10-50% range when normalized with the best-yielding region at or close to the center of the wafer." From 200 to 300 mm, that percentage has remained constant, but as growing wafer sizes put more die near the edge, it becomes a problem.

Edge inspection today is optimized for wafer — not IC — manufacturing. Available tools are usually laser scatter-based with some sort of CCD imaging technology, or rely solely on brightfield imaging technology. While these are useful to detect cracks, chips and possibly particles and blistering, defects that reduce edge yield seem more closely related to film and etch residues — things that get on the edge and flake off during subsequent processing (Fig. 2 ). Correlating these defects to die yield loss is a challenge for IC makers, but not a concern for wafer manufacturers.

2. Besides pits and fractures, the most harmful defects that seem to be affecting edge yield appear to be mostly related to film and etch residues, particles that get on the edge and flake off in subsequent processing. (Source: KLA-Tencor)

While defects of interest — edge contamination and film residues — are fairly well identified by IC manufacturers, automated detection and classification are missing. In doing inspections for edge residues, it may be that the lower bevel is the most common place of origin for a defect; however, there is no good tool for determining that. Some are using tilt SEM manual review to look at the top surface, top bevel, and sometimes the apex's upper part. However, short of flipping over the wafer (destroying its value), there is no effective way to look at the back surface or lower apex with the sensitivity needed to detect film residues and factors that may cause delamination.

Edge problems are multifaceted. A major question is how to see what is on the edge. Today, beyond the edge-specific CCD-type system, there is no ideal tool for looking at a wafer's edge or even imaging the apex; it is almost impossible with a SEM, and the backside bevel remains inaccessible. Tools are available for the front and backsides, but the edge information that can be gathered is limited. It may be possible to take photographs with a CCD and produce a map using a scatter-type tool, but understanding film composition or determining edge film uniformity requires a tool as yet uninvented.

The device maker's twin concerns — edge imperfections and particles — raise questions about what to do with them. If the particles' chemical makeup could be determined, their origin might be ascertained. The difficulty in looking at the edge (and the surface) is that, when looking at defects that scatter, sub-detector resolution may be obtainable but does not always identify the scattering mechanism. When viewing anything in a non-scattering way with optics, irrespective of how it is done, resolution is a limit.

To look at the edge, either a separate operation is required to view it directly or some way is needed to do it simultaneously. "We use a large [depth of focus] on our systems to see all the way around to the edge's tangent on one side," said Barry Bowman, director of hardware engineering at Nanometrics (Milpitas, Calif.). "Thus, we can identify things that are pixel resolution in that size. Ours is a scattering device, so we can identify particles at sub-pixel resolution by calibration, but cannot always tell what they are." This is common with scattering tools; it is difficult to determine the signature's data. It may gather specific signatures associated with pits, scratches or cracks, but it generally cannot tell a particle from a scratch or something else without some signature information. This means the topside is visible, but not the full edge. For that, it is necessary to flip the wafer and look at the edge both ways.

An option is to look at the wafer edge straight on. This stresses processing capability and, at most, only 180° can be viewed. If the whole wafer is viewed, it must be turned around to get at least two pictures. Then there is the question of the resolution at which defects can be determined. It also becomes difficult to use low-incidence light in scattering, because the edge itself becomes a scattering surface. Some rotate around the chamber to get a picture around it. However, resolution is limited by half the wavelength of the illumination light; thus, at DUV, 157 nm or so, the best obtainable resolution is on the order of 75 nm. Typically, most do it at ~1 µm, sometimes 0.8 or 0.7 µm.

Wafer manufacturers' concerns may become a subset of those of the device makers, and the answer may be along the shape of a Swiss Army knife kind of platform. The solution is not only how the tool finds the problem, but once the tool exists, how the fab manages it. How will you look, where will you look, how often will you look? Nobody yet understands how this tool would be used once (and if) it became available.