Nanoimprint Templates Need High-Quality Inspection

After almost a decade of investigation by academic and industry groups, nanoimprint lithography is beginning to gain a little traction in the semiconductor industry. Nanoimprint, simply put, squashes a 1× template into a compliant layer to create patterns on a substrate. "The amazing thing is that it has the kind of resolution that the semiconductor industry is getting very interested in — that is, well below 100 nm features, at the point where optical lithography, if it's not impossible, is becoming increasingly expensive," said Fabian Pease, professor of electrical engineering at Stanford University .

Pease was one of three panelists who participated in a technology webcast presented in December by Semiconductor International. The topic was nanoimprint lithography, and the question was whether imprint could be introduced into mainstream chipmaking — perhaps at the 32 nm node or beyond. Also on the panel were Scott Hector, manager of advanced lithography at Freescale Semiconductor Inc. (Austin, Texas); and Christopher Soles, a materials research scientist at the National Institute of Standards and Technology (NIST, Gaithersburg, Md.) and project leader for nanoimprint lithography.

As Pease pointed out, 1× technology has a bad reputation in the semiconductor industry. But he also asserts that nanoimprint is a classic disruptive technology. "The thing that makes nanoimprint different is that it doesn't need semiconductor dollars to keep it alive. And this important," Pease said. "I don't believe anyone is proposing extreme ultraviolet for any application other than large-scale manufacture of semiconductor circuits because of the enormous expense needed to keep it going. Nanoimprint is much less expensive, and there are a lot of other applications."

Pease noted several examples — including two-dimensional arrays for cell sorting, compact discs, optical polarizers and waveplates, and LEDs — of applications that the tool suppliers are already earning money on. They do not require the kind of fine precision and overlay capabilities that semiconductor manufacturing requires, but gives the suppliers the revenue they need to pursue the more stringent requirements.

Although there is no fundamental technical barrier to the 1× template, it is likely to be the most significant challenge. "It will need serious investment now both in the writing and, moreover, the inspection technology," Pease said.

Hector also sees the 1× template as the greatest challenge for nanoimprint lithography. "The great thing about nanoimprint is that what you put on the template is what you get," he said. "But that means you want the template to be as perfect as possible." It also needs to stay defect-free during use, he added, so that nothing sticks to the template and gets replicated across the wafer.

Hector showed a Pareto chart of cost elements for three different kinds of lithography (Figure ), including the cost components for producing a mask for EUV, optical immersion, and nanoimprint lithography. "What you can see is, for the optical masks, the cost is dominated by long bars for writing and inspection cost, and overall yield," he said. "Nanoimprint is dominated by inspection and overall yield. Yield is difficult because of the demanding tolerances, and inspection is much more difficult than either of the other technologies because of the fact that the features on the mask are 1×, so you have to detect smaller defects on the template."

This chart compares the relative cost of three types of lithography tools and consumables for various process steps. Nanoimprint costs are dominated by inspection and overall yield. (Source: Freescale Semiconductor)

Hector emphasized the need for an adequate inspection tool with very small pixel size and very high speed in order to make the templates. Although overlay and throughput are also challenges, the templates present the toughest hurdle, he added.

Soles also pointed to template inspection as the primary concern for nanoimprint lithography, and also presented some solutions that NIST has been working on. Two techniques — critical dimension small angle X-ray scattering (CD-SAXS) and specular X-ray reflectivity (SXR) — provide non-destructive testing with nanoscale resolutions to quantify molds and imprints.

"Defect inspection, especially in the template, is very important," Soles said. "The features are very small, it's a 1× direct-write process, and a contact lithography without protection. So you're taking this very expensive mask with very small features, and you're putting it in contact with your substrate. You need to make sure that you're not destroying that."

However, Soles offset concerns about the size of the features being inspected in nanoimprint templates with the observation that resolution enhancement features found on leading-edge optical lithography masks can also be quite small. "In fact, they can be on the order of 20-30 nm, which puts them into the realm of feature sizes that nanoimprint lithography masks may potentially have," he said. "So this argument about 1× vs. 4× masks may actually not be that big of a deal."

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