Is Reliability Compromised When You Stress Silicon?

Even though stress engineering can deliver incredible performance gain through mobility enhancement, it can also degrade device reliability. In particular, negative bias temperature instability (NBTI) degradation must be balanced with the requisite performance gain. NBTI is an important reliability concern because it leads to threshold voltage changes in pMOSFET devices.

In a recent study, Hwa Sung Rhee and colleagues at Samsung Electronics Co. Ltd. (Kyunggi-Do, Korea), together with Yihwan Kim and coworkers at Applied Materials (Sunnyvale, Calif.), studied the effects that mechanical strain has on gate oxide properties and the reliability budget for high-performance pMOSFETs. They determined that, even though compressively stressed silicon nitride films could significantly increase mobility in the pFET channel, excess hydrogen in the nitride could degrade NBTI. This degradation depends on gate length and active device width. They determined that NBTI degradation could be alleviated by using a recessed SiGe source/drain (S/D) with an elevated S/D structure.

Engineers have yet to fully understand the interaction between mechanical stress and NBTI degradation. It is generally believed that highly compressive nitride films deteriorate NBTI mainly because of hydrogen diffusion into the oxide from the nitride film, where a high density of Si-H and N-H bonds exist. But mechanical strain in the oxide may also play a role due to greater interface state generation and fixed oxide charges, which contribute to NBTI degradation.

In the Samsung/Applied Materials study, silicon nitride as a contact etch stop layer (CESL) was deposited by PECVD using SiH₄ and NH₃ source gas below 500°C over general-purpose p-channel MOSFETs, with <2 nm nitrided gate oxides fabricated using a conventional CMOS process. Intrinsic mechanical stress of the CESL film was controlled by both plasma power and the ratio of gas mixture tuning. SiGe S/Ds were formed by selectively growing 40-80 nm of in situ boron-doped SiGe with 20% germanium concentration before CESL deposition. This structure was compared to one fabricated with CESL and a silicon S/D. NBTI stress was applied with the gate electrode held at low constant negative bias (-2.0 to -2.6 V) and at 100-140°C.

In this study, when highly compressive (>2 GPa) CESL was combined with the SiGe S/D structure, the intrinsic stress was ~1 GPa, but no NBTI degradation was observed. The researchers determined that the SiGe S/D with raised S/D structure had the effect of relaxing the lateral and vertical stress and blocking the hydrogen by creating a longer path against diffusion. It also results in less performance improvement (not completely additive). In addition, NiSi creates tensile stress on the channel region. Therefore, the elevated S/D could weaken the deteriorating effect of NiSi on compressively strained channels. This elevation can make the diffusion path between the CESL and gate oxide longer. The researchers found the elevated silicon S/D does not degrade NBTI, even with a highly compressive nitride film with high hydrogen content.

In a separate study, Steve Chung and colleagues at National Chiao Tung University, Chang-Gung University and United Microelectronics Corp. (UMC) in Taiwan investigated the degradation mechanisms of devices with hybrid substrate engineering and strained silicon devices. In strained silicon devices, they found that the dominant mechanism for hot carrier (HC) and negative bias temperature degradations can be attributed to lateral electric field resulting from the mobility enhancement. But the more important finding was that for the (110)/(100) pFET/nFET devices, degradation is only weakly dependent on mobility enhancement and strongly dependent on bond strength. The group claims this to be the first report of different failure mechanisms between strained silicon and hybrid-oriented substrates.

Hybrid substrate engineering takes advantage of the higher electron mobility in (100) substrates and higher hole mobility in (110) substrates. The engineers prepared both strained Si/SiGe and (110)/(100) CMOS devices from 90 nm foundry technology. Strained silicon devices had 16 Å SiON (physical thickness) oxide on bulk silicon with different channel lengths. The (100) and (110) substrate CMOS devices had 14 Å (physical thickness) SiON oxides. Control devices were fabricated on (100) substrates.

The researchers measured drain currents and mobilities. They used an incremental frequency charge pumping method to observe HC and Fowler Nordheim (FN) stress. A gated-diode measurement was used to profile interface/oxide traps along the device channel. This method works by applying a forward bias at the drain while keeping source and bulk grounded. By applying a varying gate voltage and switching the device into accumulation, the recombination current measured from the drain terminal is regarded as the gated-diode current. Two peaks are observed: one for the FN or NBTI stress and the other for the HC-generated interface trap density in the drain junction region.

Results showed that the lateral electric field effect dominates in strained silicon devices, while the vertical field is dominant in (110) substrate devices. The larger lateral field in strained silicon devices will possibly raise reliability degradation concerns in strained silicon devices. Comparison between the HC and NBTI effects for (110) devices showed that the vertical field effect is stronger than that of the lateral field. The researchers believe its origin is caused by the weak Si-H bonds.

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