Cleaning's Role in High-k/Metal Gate Success

The International Technology Roadmap for Semiconductors (ITRS) projects that future high-performance processes will require transistor gate stacks to have an equivalent oxide thickness (EOT) of <1.0 nm for the 45 nm node.¹ As EOTs scale to <2 nm, the polysilicon gate depletion becomes a significant problem, and metal electrodes, whose depletion regions are almost nonexistent, become necessary. Importantly, when the EOT is scaled this drastically, the bottom interface quality has a significant impact on device performance. Additionally, the integration of high-k and two metals for the nMOS and pMOS transistors into the process flow is very complex. This article reviews the state-of-the-art of surface preparation before high-k deposition and of metal wet etch as part of the CMOS dual metal gate fabrication process.

The high-k gate stack represents a multilayer structure that includes a deposited high-k film and SiO₂ layer at the interface with the silicon substrate. This interfacial layer is created during surface preparation and high-k film deposition by the oxidant (ozone or water) used during atomic layer deposition (ALD) or metal-organic chemical vapor deposition (MOCVD), respectively, or by the oxidation that occurs after physical vapor deposition (PVD). The physical thickness of this oxide layer appears to be constant at ~1.0 nm;²   however, the composition and quality are highly dependent on the surface treatments before high-k deposition. Previous investigations demonstrate that the interface layer is critical for carrier mobility and EOT scaling.^3,4 The extent of differences in device performance can also depend on the method of high-k deposition.⁵

A simple approach for implementing dual metal gate CMOS is the deposition-etch-deposition method.⁶ Wet etch is the preferred method for etching the first metal to reduce possible damage to the high-k that might occur from plasma etch. The selection of the first metal is influenced by wet-etch compatibility with the hardmask and the underlying high-k material. Etch chemicals must have a minimal impact on the underlying metal and exposed high-k dielectric.⁷

We evaluated the impact of the various interface cleaning treatments (Table ) on device performance using transistors of different dimensions in a CMOS-compatible process.

The controlled in situ steam generated (ISSG) oxide etch-back process was accomplished with a continuous upflow of an HF/HCl solution in a bath. The upflow time was targeted to leave the desired thickness of ISSG oxide in the gate area. Following etch, deionized (DI) water was flowed to ensure the wafer surface was rinsed completely. After each clean sequence, wafers were transferred to the dryer module, where they received a DI water rinse and a low-pressure isopropyl alcohol (IPA)/hot N₂ dry.

As part of the investigation, some wafers received a pre-high-k deposition anneal (PreDA) in ammonia (NH₃ ).⁸ In Figures 1-3 , these steps have a -NH₃ extension.

We compared three different high-k deposition processes, which involved:

1. 3.5 nm MOCVD HfSi_x O_y films.
2. 2.5-3.0 nm of HfO₂ films deposited in an ALD reactor, using 40-55 alternating cycles of HfCl₄ (transported from a solid source using a carrier gas) and H₂ O oxidant.
3. 3.0 nm of HfO₂ deposited in a different ALD reactor, using 38 cycles of tetrakisethylmethyl-amino hafnium (TEMAHf) and O₃ oxidant.

After high-k deposition, all wafers were immediately treated with a post-high-k dielectric deposition (with NH₃ anneal) as part of a sequenced recipe. The TiN/polysilicon gate electrodes were formed using CVD of NH₃ and tetrakis (diethylamido) titanium (TDEAT) to deposit 10 nm of TiN. Then we deposited 180 nm of undoped amorphous-silicon using a silane-based RTP CVD process. The polysilicon was doped by ion implantation. All gate stacks described in this work received a source/drain (S/D) anneal. We used the North Carolina State University CVC model⁹ to calculate EOT and mobility.

In general, we found that leakage current density increased exponentially with decreasing EOT for the ozone-, SC1- and ISSG-based cleans that preceded MOCVD deposition. The data show that the EOTs have a direct correlation with the starting interface thickness: thinner films led to thinner EOTs. The NH₃ predeposition anneal had little effect on leakage, but caused the EOT values to shift lower by 0.6-1.4 Å less than similar splits without the PreDA.

Figure 1 shows the effective electron mobility as a function of EOT at a high field value (1.0 × 10⁶ V/cm) for the same wafers. The data represent up to five sites per wafer, and are generated from the NCSU mobility model. The high field mobility is reduced as EOT is reduced. A trend line through the majority of the data indicates that three points show significantly higher EOT and poorer mobility. These points correspond to the SC1 process (with and without the NH₃ PreDA) and NH₃ PreDA of the O₃ chemical oxide. This suggests that the interface created with the SC1 chemical oxide is significantly inferior to any of the other tested interfaces. The NH₃ anneal directly affected the O₃ chemical oxide, causing mobility to plummet.

1. The HfSixOy MOCVD films that underwent predeposition anneal resulted in lower calculated EOT values, but reduced mobility.

ALD of HfO₂

We observed similar trends with the H₂ O-based ALD HfO₂ wafers. Leakage currents decreased with increasing EOT, and EOTs had a direct correlation to the starting interface thicknesses. The mobility values again increase with EOT (Fig. 2 ). The wafers with the highest mobility values started with the thin-etched ISSG interface, suggesting that the etched ISSG interface is of higher quality.

2. Mobility decreases with increased EOT for these H2O-based HfO2 ALD films. The highest-quality film uses a thicker high-k layer.

The main difference with the O₃-based ALD HfO₂ wafers is that the NH₃ PreDA wafers did not have lower EOT, but did have lower mobility. This may have been caused by the oxidizing nature of the O₃ precursor used for high-k deposition. The splits with the NH₃ PreDA did have reduced leakage, suggesting that some modification to the interface occurred.

Again, the high field mobility was reduced as the EOT was reduced (Fig. 3 ), but the effect of the NH₃ PreDA was much more pronounced. A logarithmic fit to the data shows a significant decrease in mobility value for both data sets as the EOTs decrease. As the EOTs increase and the ISSG interface becomes thicker, the mobility increases to a value equal to an ISSG oxide without high-k. At low deposition temperatures, either the chemical or thermal SiO₂ layer initially grown on the silicon substrate can limit additional growth of the interfacial layer during high-k deposition. Both oxides may provide an effective barrier to further oxygen diffusion since oxygen usually diffuses more in high-k films than in SiO₂. This suggests that the thinner interfacial oxides are more susceptible to modification during high-k deposition and subsequent processing.¹⁰

3. Mobility decreases significantly as EOT decreases for these O3-based HfO2 ALD films.

Metal etch

As part of the integration process, removing metals selective to the high-k dielectric is necessary (Fig. 4 ). After dry etch to remove the unwanted mask material, the exposed candidate material has to be etched using selective wet chemistry without affecting the underlying high-k layer; the remaining mask material must then be removed without attacking the remaining candidate metal and the exposed high-k layer. High-k removal and roughening must be minimized to prevent device degradation.

4. The first metal etch step must completely remove the metal without damaging the high-k dielectric. The hardmask removal step needs high selectivity to the underlying metal and high-k.

We studied various chemical mixtures and their effects on different candidate mask and high-k materials and their compositions. These mixtures included SC1 (DI:H₂ O₂ :NH₄ OH), SC2 (DI:H₂ O₂ :HCl), H₂ O₂, HCl, SPM, NH₄ OH, and HF with different compositions at different times and temperatures. The candidate metals included TiN, Ta, TaN and TaSiN; the mask materials included TEOS and amorphous-silicon; and the high-k materials were ALD HfO₂ and HfSi_x O_y.

We determined that SC1 could etch TiN, TaN and TaSiN; HF could etch Ta, TaSiN and the TEOS hardmask material (Fig. 5 ). SC1 was chosen as the metal etchant of choice because of its high selectivity to the hardmask and high-k materials. HF was chosen to remove the TEOS hardmask. Although the HF did not impact exposed HfO₂, it aggressively attacked exposed HfSi_x O_y. Therefore, we decided to use amorphous-silicon as a hardmask, which is impervious to the SC1 metal etchant and can be easily removed with NH₄ OH without attacking any of the metal or high-k materials. Metal and high-k films processed through representative metal and hardmask removal processes have a smooth surface and show no impact from exposure to the chemicals.

5. Based on these selectivities, SC1 was chosen as the etchant for the metal, and amorphous-silicon as the hardmask.

We fabricated devices through a CMOS-compatible process with a TaSiN/TaN metal stack. The capacitance-voltage and current-voltage curves for the capacitor wafers with and without wet-etch processes were well behaved; the differences can mostly be attributed to the slight 1.7 Å EOT difference between the nMOS and pMOS regions of the underlying gate dielectrics. Thus, some additional optimization is required.

The integration of high-k and dual metals for nMOS and pMOS into the process flow is complex. There are various approaches to achieving the high-quality interface required before high-k deposition. The need to reduce EOT appears to preclude achieving mobility values equivalent to SiO₂ using current technologies.

A high-k device fabricated on an HF-last prepared substrate will have different EOT and electrical properties than a device fabricated on an HF-last substrate annealed in NH₃ ambient. This is because of the different effects each has on the SiO₂ interface grown during high-k deposition. The properties of these interfaces also differ from that of an SiO₂ interface produced by a chemical clean or thermal oxidation.¹¹

The use of NH₃ anneals on HF-last surfaces incorporates nitrogen into the interface, reducing EOT and degrading mobility; thicker interfaces created by O₃ chemical oxidation or controlled etch of an ISSG oxide improve mobility slightly but at the expense of EOT. However, when compared to the chemical oxide interfaces, the ISSG interfaces scaled appropriately and exhibited better overall electrical performance. This is attributed to the thermally grown interface in ISSG.

Differences in device performance also depend on the method of the high-k deposition; oxidizing ALD reactants appear to lead to overall higher mobility on all thin interfaces. Although numerous researchers are evaluating non-traditional gas and surface chemical treatments, increasing the quality of the interfacial oxide appears to be the best approach at this time.

Proper selection of the hardmask and wet chemical etchants are critical to high-k/metal gate integration. The use of an amorphous-silicon hardmask and an SC1 chemical mixture may be a potential solution.

Follow-up work on this study, including the removal of high-k residues, will be presented at the ECS-SEMI Fifth International Semiconductor Technology Conference in Shanghai March 21-23.