Room-Temperature Through-Hole Bonding

Stacked-die system-in-package (SiP) devices have been around for quite awhile, saving board space in a variety of ways. An approach for making stacked SiPs and 3-D ICs that is receiving more attention is the use of through-hole contacts, as evidenced by the half dozen papers presented on the subject at this year's ECTC in Lake Buena Vista, Fla. In one of those presentations, researchers at Hitachi and Renesas Technology (Tokyo) presented a through-hole electrode technique that forms interconnection between stacked die at room temperature.

Through-hole contacts are receiving more attention because they increase interconnection density, decrease wire lengths, and save space. The most popular approach currently is the simple stacking of die, with wire bonds connecting them to a common substrate and sometimes each other. This approach is good for applications that require a few die. The limits of this approach are reached when there are several die, for which multiple wire-bonding techniques are required to produce an intricate arrangement of many wire bonds.

In other cases, ultrathin packages are stacked on each other within a package. This approach has reliability and cost advantages, and its interconnection density is sufficient for today's applications. Through-hole contacts can provide the increased interconnection density between die required by upcoming applications, and they can help reduce package size even further. The process presented by Hitachi and Renesas achieves these goals by pushing gold stud bumps from one die into the gold-plated through-holes of another die.

The wafer that is to have the through-holes is bonded facedown onto a glass handle wafer using a removable UV-cure adhesive. The wafer is thinned down to the 30-50 µm range, and the 25 µm diameter through-holes are etched using reactive ion etching (RIE) until the front-side contact pads are reached. Next, a 2 µm layer of oxide (SiO₂) is deposited using PECVD at 100°C, and the oxide at the bottom of the hole is etched to expose the contact. After chromium barrier and gold seed layers are sputtered, the holes are electroplated with gold. Wet etching then defines the land area of the electrodes.

The matching contacts on the other wafer are simply gold stud bumps. The connection process is a simple matter of pushing that wafer onto the through-hole wafer with enough force to make the bumps deform and "flow" into the through-holes (Figure ). This process, performed at room temperature, was enough to make contacts with sufficient conductivity and reliability. Since the coefficient of thermal expansion (CTE) for gold is higher than that of silicon, heating only makes the contact better.

Gold stud bumps are forced into gold-plated through-hole electrodes to form die-to-die contacts.

Using this process, the reserachers bonded a 50 µm thick SDRAM chip to a 30 µm thick microprocessor, with a 30 µm thick silicon interposer between them to help reduce warping of the thin die. The 20 µm spaces between the die, and the space between the microprocessor and the package substrate, were all encapsulated with an underfill material. No other encapsulation was used, and the overall thickness of the SiP was less than 0.5 mm.

In addition to the advantages of having a thinner, smaller package, having shorter signal paths between die make it possible to improve the system's performance. Not only is it possible for the system to run faster, it also wastes less power. Wire length is a major concern when it comes to power usage, and keeping wire lengths short goes a long way toward keeping power use down. Much of the concern about using stacked-die packages and 3-D ICs is about heat removal, but much of that concern comes from experiments done on die connected only on the edges. The use of through-hole contacts reduces the overall wire length, which can reduce heat generation.

This package is representative of the target product for this process: off-the-shelf processor and memory die possibly combined with an ASIC. This provides the opportunity to bring new products to market quickly, using a process whose overall cost is likely to be comparable to that of established packaging processes.

Down the road, it will likely be desirable to stack several die this way; either to make a complex system out of many off-the-shelf parts, or to assemble a single IC out of several component die. A process like the one presented here holds the promise of making such a device with comparatively inexpensive processes.

As the industry continues to pursue the dictates of Moore's Law, it is becoming more clear that reducing transistor sizes is not enough. Reducing or sidestepping the performance, power and cost limitations imposed by interconnects at all levels will be necessary. Processes like this one are not just about packing more functionality into smaller spaces. They are about keeping interconnect costs and limitations down as well, and these will likely be the key costs and limitations to address in the near future.

For more information on semiconductor packaging, go to www.semiconductor.net/packaging.