Improving Defect Capture Rate for Excursion Detection

In an advanced 300 mm semiconductor fab, a product wafer's potential worth has increased by many times because of the transition to larger wafer sizes and aggressive shrinking of design rules; thus, rapid and continuous yield improvement has become increasingly critical to any fab's success.
 
Advanced fabs typically have several hundred process steps and weeks of cycle time. To minimize product risks at final test, inline defect inspection is used to measure and collect defectivity levels on product wafers at key inspection steps during both process development and high-volume manufacturing phases. One of the most important means to achieve high yield is an effective, fabwide inline product inspection strategy.

As the industry moves toward increasing levels of integration and reduced product lifecycles, a close examination of the cost associated with wafer inspection is required. It is well established that most, if not all, semiconductor manufacturers use one or more of the available wafer inspection technologies as part of their defect inspection and control plan. The sample plans (number of lots inspected, number of wafers per lot inspected, and wafer coverage) are strongly affected by the inspection technology (high vs. low throughput) and the production phase (development vs. production). An effective yield learning and improvement program that includes comprehensive inline defect inspection techniques with maximum wafer inspection efficiency will help minimize the cost associated with wafer inspection. Naturally, this should not compromise critical defect detection and excursion capture, both vital for rapid yield learning and to sustain performance over time.

For this experiment, the KLA-Tencor Sample Planner program was used to optimize the inspection sampling plan by prioritizing the inspection layers that are critical for excursion control. The program was also leveraged to assess the impact of the capture rate of a defect type on the overall cost associated with wafer inspection.

Powerchip Semiconductor Fab 12A (Hsin-Chu, Taiwan) currently performs inline inspection for 32 process layers using brightfield and darkfield detection tools. As a first step of Sample Planner optimization, defect data analysis is performed to determine critical parameters such as variance ratio, defined as the ratio between lot-to-lot variance and wafer-to-wafer variance; excursion frequency, or the number of lots between excursions; the fraction of materials at risk; and the normalized defectivity (number of defects) mean shift. The mean shift is defined as the difference between the out-of-control (OOC) defectivity mean and the in-control defectivity mean, normalized to the defectivity standard deviation. The Table shows defect data analysis results for the 32 inspected layers. Six months worth of historical defect data from inline inspected production lots was used for the analysis.

Sample Planner cost analysis

Many IC manufacturers tend to view defect inspection tools as a non-value-added proposition. As such, they are not inclined to invest much time and effort in planning their inspection capacity as part of a fabwide inspection strategy. The Sample Planner cost model program,^1-3 a combination of advanced statistical and stochastic models, provides the framework and tools to analyze critical fab parameters to develop an optimal inspection strategy.

Maintaining a balance between sensitivity (reduced time to excursion) and throughput (reduced inspection costs) is very critical in enhancing inspection efficiency and reducing the amount of product at risk. Figure 1 shows a simple example of how increasing the inspection frequency will reduce excursion cost because excursions are caught faster. But inevitably, the inspection cost rises with increased inspection frequency. The goal is to reach that optimum point at which excursion and inspection costs are both kept at a minimum.

1. While increasing inspection frequency reduces excursion costs, it will raise inspection costs. An effective inspection strategy must strike a balance between reducing risk to the product and minimizing the inspection cost. (Source: KLA-Tencor)

In addition to the defect data analysis parameters already discussed, other fab and inspection parameters — such as the die adjusted selling price (ASP), the number of wafer starts per week, the starting defect density, inspection time, and the lots and wafer sampling — are employed as input data in the Sample Planner cost analysis.

Using the applicable data inputs already listed, the value of materials at risk (excursion cost) per week is estimated using the Sample Planner. Numerous results in sample planning analysis have shown that effective inspection capacity optimization is dependent on the value of the materials at risk.^4,5 A trade-off is often needed for a balance between the cost of inspections — including fixed and variable costs — and the cost of yield loss caused by undetected defect excursions.

The main parameters that were optimized are:

• Inspection layer insertion in the process flow.
• Inspection frequency (percentage of lots to inspect, number of wafers per lot, and wafer inspection area).
• Inspection sensitivity or defect capture rate.
• Defect to track for excursion monitoring.
• Inspection capacity allocation.

For analysis, a model was constructed with certain assumptions and inputs:

• Only the impact of excursions is used; baseline defectivity is assumed to remain constant, so any benefit gained in reducing baseline defectivity is excluded.
• All critical defect types are generated at the current layer (adder defect).
• The frequency of occurrence is defined as the probability that when an excursion event takes place, it is because of the defect of interest.
• The total inspection cost is the sum of the excursion cost, the cost of false alarms, the cost of investigating/fixing a problem caused by an excursion, and the inspection tool cost.
• The inspection tool cost includes capital depreciation, manpower, service/parts, and facilities.
• The excursion cost or excursion revenue cost is the value of the die that cannot be sold because of the lower yield on wafers affected by excursion.

Figure 2 shows the results of Sample Planner analysis used to prioritize the inspection layers using their respective excursion costs. Only the top 10 layers with the highest excursion costs are shown.

2. Based on their respective excursion costs, Sample Planner analysis prioritized the results charted. Here, the revenue/cost shown on the charts’ Y axis is given by week. (Source: KLA-Tencor)

Also, various sampling scenarios were used to identify the optimum sampling plan to minimize overall inspection cost, based on selected layer, variance ratio, and inspection tool sensitivity (Fig. 3 ). The optimum sampling plan in this case consists of 33% lot sampling.

3. Optimum sample with 33% lots vs. current with 25% lots. (Source: KLA-Tencor)

Defect capture rate assessment

In most cases, inspection tools are introduced when a new product technology is launched. At any inspection level, the sensitivity used for a particular inspection tool is optimized to maximize capture of killer defect types. A high percentage of the critical process layers is inspected to identify new defects and understand their root cause and impact on yield. This is essential for rapid defect learning and yield improvement and, during this phase, a high-sensitivity tool is often required with throughput as a secondary concern. However, as the product technology matures and moves to a production phase, the choice of inspection technique should be linked to the capture rate of the defect of interest and its yield impact.

Effective yield learning and improvement program tool selection must be combined with an understanding of the defect yield impact. The inspection tool must be sensitive to the defects of interest, and the defect must have an impact on yield. It is crucial that yield engineers have an appreciation of the defects' yield-limiting potential, and that their kill ratios are validated on a regular basis as new products, processes and equipment are introduced. The root cause of all critical defects should be identified and their yield impact known or estimated.

For example, studies on the effect of defect size on yield impact show that the highest yield impact stems from defects that are 1.5× the minimum design rule spacing;^6,7 therefore, any inspection tool used at an inspection level should provide even better sensitivity to capture yield-limiting defects. Also, for maximum wafer inspection efficiency, yield engineers should understand their inspection tools' sensitivities and capabilities. By selecting the right tool for specific defects of interest, they can reduce costs associated with capturing non-critical defects, without impacting yield or missing critical killer defects.

Sample Planner was used to assess the impact of the capture rate of a defect type on the overall cost associated with wafer inspection and the defect excursion impact. The Sample Planner modeling cannot improve capture rate, but uses the capture rate as an input to account for its effect on overall cost. The capture rate of a tool for a defect type then becomes a measure of the tool's effectiveness.⁸

One specific process layer (SiN etch back) was used in the analysis as an example emphasizing the importance of the defect capture rate for defects with high yield impact. Figure 4 shows the defect type Pareto for the three critical defects with the highest yield impact at this layer (40%, 20% and 10%).

4. The three critical defects of interest are pattern open, indentation and pattern short with an estimated yield impact of 40%, 20% and 10%, respectively. A total of four lots were used. (Source: KLA-Tencor)

Figure 5 shows the excursion cost as a function of the capture rate for three critical defects: pattern open, indentation and pattern with a yield impact of 40%, 20% and 10%, respectively. The yield impact percentage for each defect is shown in brackets. The delta excursion costs (5-100%, capture rates) were $448,384, $100,683 and $158,000 for a yield impact of 40%, 20% and 10%, respectively. The result could steer yield engineers toward an inspection tool with high sensitivity to their specific defect of interest, rather than to the total defect count.

5. Excursion cost vs. capture rate for pattern open, indentation and pattern defects with different yield impacts. (Source: KLA-Tencor)

The following benefits of using Sample Planner for inline inspection implementation and overall wafer inspection strategy were demonstrated:

• Assessment of inline inspection strategy and defectivity excursion impact.
• Prioritization of inspection layers based on their defect data analysis. A dynamic sampling could be used to increase or decrease sampling depending on the variance ratio and/or excursion frequency.⁹
• Prioritization of inspection layers based on their excursion cost.
• Assessment of defect capture rate to help balance sensitivity (high capture rate) and throughput (low capture rate) criteria, depending on the defect's yield impact.

Sample Planner cost analysis was used to provide an optimized sampling plan based on excursion costs and lots at risk for Powerchip Fab 12A's current defect excursion rates, cost parameters, wafer starts, and inspection capability. The recommendations that resulted from the analysis include the percentage of lots inspected increasing from 25% to 33%, and increasing the area inspected from 25% to 50% on layers with high excursion cost. Increasing the area inspected increases the spatial signature detection without significantly affecting total inspection cost.