Well Into the World of Nanoelectronics

Nanotechnology is an overused and often confusing term. For instance, if you define nanotechnology as any device with feature sizes below 100 nm, "we are well into the world of nanoelectronics," said Alain Diebold, senior fellow at Sematech (Austin). But if you define nanotechnology as only atomic in-scale structures with a novel modus operandi — as Curt Richter, head of the nanoelectronic device metrology project at NIST (Gaithersburg, Md.), does — only things like quantum devices, molecular electronics and organic thin-film transistors apply. When it comes right down to it, there is a bridge between top-down nanoelectronics, beginning with sub-100 nm CMOS-based devices, and bottom-up nanostructures with novel properties and functions. One big difference is the electrical behavior of nanostructures is dictated more by interface material properties than bulk properties, and CD greatly impacts threshold voltage of nanodevices, "which is really the key thing we need to worry about below 10 nm, where metrology precision needs to be on the order of atoms," Diebold said.

Diebold and Richter were joined by Bryan Rice, EUV engineer at Intel (Hillsboro, Ore.), for Semiconductor International's most recent technology webcast, "Metrology in the Nanotech Era ". They addressed the roles of CD-SEM, scatterometry, AFM, TEM holography, FTIR and other metrology methods. For example, TEM holography has the capability to detail a small void in a TiO₂ film (Fig. 1 ).

Rice analyzed the extension of the industry's tried-and-true metrology methods, CD-SEM and scatterometry, for the 32 nm and future nodes. For the 32 nm node, there is a need to measure 18 nm gates in resist and 13 nm features after etch. The contacts are ~40 nm in resist with a 32 nm half-pitch. Both profiles and CDs are critical. "After sending structures to various materials suppliers, we have found that CD-SEM has not run out of gas yet. Precise CD measurements are possible," Rice said.

1. TEM and 3-D holography resolve an internal void in a TiO2 particle. Electron phase shifts are sensitive to variations in mean inner potential (thickness) and electro-magnetic fields. (Source: NIST)

Rice was slightly less confident about the extendibility of scatterometry, although he said it is capable of measuring CDs down to 20 nm, and there is good correlation between scatterometry and CD-SEM measurements. "The biggest issue is scatterometry's sensitivity to small features because, as CD shrinks, the spacing between adjacent spectra is getting smaller and smaller, but this is something the suppliers are actively working on," he noted.

Richter said, "NIST focuses on building blocks such as silicon nanowires or nanodots. Our goal for developing nanoelectronic test structures is to enable the reliable, reproducible measurement of nanocomponents." The program is designed to develop robust test structures and accompanying electrical test protocols, and then to electrically characterize atomic scale structures. "Everyone wants this dream of knowing where every atom is at exactly. For instance, in a trigate FET, we need to determine and monitor the size of the wire; know the dielectric film thickness around the wire; and monitor the dopant profile, which is very challenging when few dopants exist," he said.

"Some of the more spectacular results have been imaging hafnium atoms at the interface between the high-k dielectric and silicon channel using aberration-corrected lenses in TEM," Diebold said. An aberration-corrected TEM of a silicon nanowire (Fig. 2 ) shows the twinning structure (straight lines) and the gold dot that served as a catalyst for growth of the nanowire (lower right). The amorphous portion is the carbon film that holds the TEM sample. "We're also looking at the impact of electron diffraction as another metrology technique that is key to understanding nanotechnology," Diebold said.

2. Modeling plays an important part in nanometrology. An aberration-corrected nanowire image shows the gold dot structure used to grow the nanowire and nanowire twinning. (Source: Sematech)

Richter added, "In the short term, for metal gates in CMOS, we can look at ultrathin high-k gate dielectrics using backside FTIR. This has demonstrated monolayer sensitivity."