Aligned Wafer Bonding for 3-D Interconnect

One of the major challenges in the IC industry for further enhancing Moore's Law is interconnect technology. While scaling of planar CMOS ICs combined with copper/low-k interconnect technology continues to drive productivity enhancements in integrated electronics, scaling beyond the 45 nm technology node is projected to be increasingly expensive and difficult. Even the most innovative first-level single-chip and multiple-chip packaging approaches can limit IC performance capabilities and increase product cost.^1-3

A critical challenge in interconnect technology is global interconnectivity (e.g., clock distribution).⁴ Stacking of functional modules, such as logic and memory or logic and sensor elements with through-die interconnectivity, reduces the length of these critical connections from millimeters to microns, thereby reducing the related interconnect delays significantly.

Aligned wafer bonding is a wafer-to-wafer 3-D interconnect technology where the wafers are aligned and bonded face to face or back to face, and then thinned and interconnected prior to additional stacking processes or dicing (Fig. 1 ). Wafer bonding and wafer-to-wafer alignment are well established technologies from MEMS manufacturing, but they require process and equipment enhanced to provide the compatibility with back-end CMOS IC wafer processing, as well as micron-size through-die interconnectivity needed in 3-D ICs.

1. In aligned wafer bonding, wafers are aligned and bonded, then thinned and interconnected before additional stacking processes or dicing.

In addition to the performance advantage of reduced interconnect delay and reduced interconnect parasitics, wafer-level 3-D integration reduces the manufacturing complexity. For example, high-performance microprocessors include an ever-increasing amount of on-chip memory. 3-D integration through aligned wafer bonding will allow for manufacture of the memory on a separate wafer with optimized processing (e.g., the wafer only needs to be processed through the mask levels that are required to manufacture the memory). This partitioning enables a more cost-effective manufacturing process at higher yields. Heterogeneous subsystems like ASIC and MEMS devices often require vastly different, sometimes excluding, process steps. Aligned wafer bonding enables heterogeneous functional stacks, such as logic with memory, mixed signal, or wireless transceivers. Also, heterogeneous material combinations such as silicon with compound semiconductors are possible. New devices that incorporate complex sensing elements, signal processing, logic functions, a memory with a program, and reference values and outputs will be possible. The high bandwidth that is offered by 3-D integration will allow for parallel processing of data (e.g., of an image sensor). Standardization of building blocks, such as processing unit, memories, I/Os, sensing arrays, etc., will enable a broad variety of devices with a fast time to market at a competitive cost.⁵

While 3-D die packaging (or system-in-package, SiP) is used in portable electronic applications, such as cell phones, to reduce the footprint required for ICs, the high inductance from the wire bonding at the edge of the die to the PCB limits performance and I/O density. We focus on approaches that provide micron-scale, low-parasitic, high-density vertical interconnectivity and compare the die-to-die (die-level), die-to-wafer, and wafer-to-wafer (wafer-level) approaches. Die-to-die approaches require pick-and-place machines to properly align prefabricated vertical interconnects; a bonding process is required that provides sufficient bonding strength (critical adhesion energy) and electrical interconnection with sufficiently low specific contact resistivity. While this approach has a key advantage in that known good die (KGD) can be used, the low throughput and positional accuracy requirements with various die sizes are a limiting factor. Moreover, very high-aspect-ratio (HAR) vias are needed to achieve micron size, since the thicknesses of the bare die are greater than ~20 µm. While this approach is useful in demonstrating the performance advantages of such through-die interconnectivity, the HAR via requirement and manufacturing throughput constraints favor die-to-wafer and wafer-level approaches. This is particularly true when extensions to three or more die in a vertical stack are considered. Die-to-wafer approaches use pick-and-place machines with the first-level wafer as a substrate. Such an assembly process can incorporate KGD in the second and higher levels, with die yield a factor only in the first-level host wafer. Most importantly, die can be smaller and specific IC enhancements can be incorporated in smaller manufacturing quantities. The die-to-wafer approach is a viable approach to 3-D, which will go into production soon.⁶

Wafer-to-wafer provides the lowest manufacturing cost 3-D solution for large quantities. However, the integration must consider die yield, identical-size die requirements and wafer-level compatibility of the bonding and thinning processes. Die yield, as well as thermal constraints inherent in 3-D integration, are addressed later in the article, but both can be addressed by proper design partitioning.

Key processing challenges for a back-end compatible wafer-level 3-D platform include:

• Precise alignment of full wafers (≤1 µm accuracy).
• Thin adhesive-layer bonding at low temperature (≤400°C).
• Precision thinning and leveling of top wafer (~1 µm thick).
• Inter-wafer connection by high-aspect-ratio (>5:1) vias.

The most differentiating process steps are the wafer-bonding approach and the inter-wafer interconnect processing. One differentiator is via first or via second, depending on whether the inter-wafer vias are fabricated before or after bonding, respectively.

The Rensselaer approach for a wafer-level 3-D technology platform is depicted in Figure 2 for a three-wafer stack. Two fully processed wafers are aligned face to face (or interconnect structure to interconnect structure) to tolerances within 1 µm and bonded using a dielectric adhesive that is compatible with CMOS processing and packaging. The top wafer in the two-wafer stack is thinned to ~1 µm by backside grinding, chemical mechanical polishing (CMP) and selective wet etching to an etch stop (e.g., an implanted layer, a graded SiGe epitaxial layer, or a buried oxide [BOX] layer with SOI wafers).

2. Schematic of 3-D interconnects using aligned wafer bonding.2,3

Subsequently, bridge-type and/or plug-type inter-wafer interconnects (Fig. 2 ) are formed using a copper damascene patterning process, developed jointly by Rensselaer and the University at Albany. Repeating this process flow, additional wafers can be aligned, bonded, thinned and inter-wafer interconnected. This approach does not require handling wafers, as thinned silicon is not transferred. Most proposed applications require two- or three-wafer stacks.

There are three major approaches for wafer bonding for wafer-level 3-D integration. Both direct oxide bonding and dielectric adhesive bonding use a via-second process, while metal-to-metal bonding uses a via-first process flow.

The first approach is direct oxide bonding at low temperature, which requires good nanoscale planarization and surface roughness control with proper surface activation. Direct bonding recently gained more interest because of the development of wafer-surface plasma activation, which enables reduction of the annealing temperature to <400°C. The sensitivity to particles and surface warp makes this approach more amenable to bonding of wafers with only lower levels of IC interconnect structures.^7,8

The second approach is metal-to-metal bonding, where the metal bonds also serve as inter-wafer interconnects; copper bonds, solder or micro bumps have been utilized, with the latter approaches involving wafer-level packaging-like technologies. Wafer non-planarity can be a negative factor in obtaining within-wafer uniformity. Recently, Morrow et al. reported that they have achieved a wafer-level Cu-Cu 3-D integration approach capable of delivering yields required for high-volume production.⁹

Lastly, there is dielectric adhesive bonding using curable polymers, polyimides or other adhesives, where the dielectric adhesive can accommodate wafer non-planarity, submicron-sized particles and some processing-induced stress.^2,3,10

The Rensselaer baseline bonding adhesive is benzocyclobutene (BCB), which is used in packaging applications as a stress buffer and has been used as an interlevel dielectric in GaAs ICs. Figure 3 depicts a two-level copper interconnect test structure processed at Sematech after bonding to a trichloroethylene-matched glass wafer and removal of the bulk silicon using the three-step thinning process. Although the surface profile shows a step of ~850 nm across the aluminum bond pads, void-free bonding is obtained after bonding and maintained after the thinning process. The interconnect structures are completely damage-free with this process, and even maintain structural integrity after grinding and polishing through the bulk silicon.

3. Semi-transparent copper/oxide-interconnect wafer bonded to a glass after removal of silicon substrate on a Sematech wafer. Though the surface profile (right) shows a step height of ~850 nm across the aluminum pads, void-free bonding is obtained and maintained after wafer thinning.15

The investigation of the correlation between BCB layer thickness and bond strength revealed that the critical adhesion energy increases linearly with BCB layer thickness. But even thin BCB layers starting from 0.4 µm thickness achieved sufficiently high bond strength, enabling reasonable aspect ratios for the inter-wafer via interconnects.¹⁰ The bottom wafer of the wafer stack gave mechanical support during the back thinning of the top wafer. Therefore, no handling substrates are required, which keeps the process flow simple.

The copper back-end interconnect structures have been analyzed in-depth. Both electromigration tests as well as performance tests (via chain resistance and surface leakage current with comb-like structures) were conducted. While some degradations in via-chain and surface leakage were observed, particularly with the copper/ultralow-k structures, the final results were considered mostly within specification. There was no attempt to reduce process-induced stress with the copper/ultralow-k structures; we believe the small degradations observed can be reduced with further process refinement. Electromigration data was similarly promising.

4. Focused ion beam cross-section of CMOS SOI wafer after double bonding/thinning, BCB ashing and sawing. 3,11 (Source: Freescale)

Similar electrical tests have been done using 130 nm technology node, CMOS SOI wafers with four levels of copper/low-k interconnects.³ Results indicate very little change in ring-oscillator delay, n-FET and p-FET threshold voltage and n-FET and p-FET subthreshold voltage leakage. A focused ion beam cross-section of the interconnect structure, active silicon layer and BOX layer of the original wafer, bonded with a ~2.1 µm thick BCB to a prime silicon wafer is shown in Figure 4 .

Mechanical and thermal testing of the bonded stack included conventional sawing of the double-bonded and thinned wafer pair and conventional die packaging reliability tests (autoclave for 48 and 144 hours and liquid-to-liquid thermal shock). No degradation in critical adhesion energy of the BCB was observed in four-point bending measurements at Rensselaer Polytechnic Institute, and die-handling characteristics were very similar to conventional die. To summarize, the achieved results show that wafer bonding using BCB is fully compatible with CMOS processes and back-end-of-line (BEOL) packaging.¹¹

Wafer-to-wafer alignment

High-precision alignment is an enabling technology for 3-D interconnects. The higher the alignment accuracy, the lower the silicon real estate consumption required for the interconnects. Moreover, the alignment accuracy must be maintained during the bonding process.

Wafer-to-wafer alignment using infrared light allows a real-time control loop for the alignment process. Silicon gets transparent for wavelengths above 1050 nm, but the transmissivity decreases with the concentration of dopants. Metal layers cannot be used in the area of the alignment keys. This method is best suited for two wafer stacks, because contrast and resolution are decreased in multi-layer systems because of multiple reflection and diffraction effects. Bottom-side (or backside) alignment, now the industry standard for MEMS wafer bonding applications, is not applicable for 300 mm CMOS applications, as they are strictly based on single-side processed wafers.

A new method, the SmartView face-to-face alignment, allows using visible light for alignment keys of both wafers within the bond interface. It uses dual microscopes with identical optical axes. One microscope is placed above and the other below the wafer stack. The alignment capability is not impacted by the dopant concentration and metal layers and fulfills the requirements for multi-wafer stacking.

Wafer-level 3-D IC technology is a significant addition in IC processing that could reduce the complexity of subsequent packaging. While the individual process steps of submicron wafer-level alignment, wafer-to-wafer alignment, wafer thinning to ~1 µm and inter-wafer interconnection are within IC process capabilities at this time, all such processes must be introduced simultaneously. For commercial markets, this would be either at a given technology node or a specific large-volume market (e.g., smart imagers with pixel-by-pixel processing). While 3-D design tools that properly account for parasitic coupling and signal integrity issues are needed, their development is considered within current capabilities.

A key issue is thermal management, which is already limiting high-performance processor design. However, by proper design partitioning, the thermal constraints can be relaxed, particularly with extra copper inter-wafer interconnects for thermal flow (as well as electrical grounding).¹² Another key issue for wafer-level 3-D is die yield. Unlike die-to-die and die-to-wafer 3-D implementations where KGD can be used, wafer-level 3-D implies a yield hit. However, with proper partitioning, the yield hit can be minimized, and might even improve. For example, the L2 cache in the upper wafer(s) can be of high yield, particularly with error-correcting designs, while the processor, L1 and small L2 cache die area will be smaller than that of a larger die for an SoC with large L2 on-chip cache. Since yield is a function of area, the 3-D implementation could have higher yield.¹² This advantage can be expected to grow with future technology nodes as the processor-to-memory area ratio decreases. A key limitation is time-to-market of new IC designs and with component die scaling within a technology node.