2005 ITRS: Analyzing Smaller Defects Faster

With increasing process complexity and fewer learning cycles with each new technology generation, it is impossible to achieve historic yield ramps and mature yield levels without better tools and methodologies. This is the main reason why ongoing breakthroughs in yield modeling, defect detection and characterization, contamination control, and yield learning are so important in device manufacturing.

The 2005 International Technology Roadmap for Semiconductors (ITRS) identified the No. 1 challenge with yield enhancement as the ability to detect defects of sizes that scale as quickly or faster than the device features scale, which requires greater sensitivity — something that traditionally has gone hand-in-hand with lower-throughput tools. This is a trend the industry needs to change.

In its summary, the ITRS working group that focuses on yield enhancement emphasized needs for many of the tools and technologies it has called for in past revisions: defect inspection tools that find smaller defects and can sort the yield-relevant defects from nuisance defects; faster, more cost-effective tools for inspecting high-aspect-ratio vias and contacts; faster inline chemical analysis tools for light elements (alternative to EDX); better test structures and data management for root cause analysis; and systematic yield loss diagnostic capability. Inspection systems must be able to differentiate between different killer defects at a high capture rate and throughput. In addition, there is an ongoing need to correlate contamination levels in fluids and gases with product yield to establish control limits rather than simply always calling for higher and higher purity materials. Finally, a very ambitious but important goal is to develop parametric-sensitive yield models that can be used with new materials and patterning methodologies, such as optical proximity correction (OPC). The Table summarizes the difficult challenges that must be overcome between now and the year 2013 approximately (32 nm implementation).

Once the working group summed up these important priorities, they tackled some new requirements that are making their first appearance in the 2005 roadmap. Because the bevel and edge region of the wafer has become an area of increasing yield impact, existing tables on defect inspection tools were extended to include specifications and requirements for a new type of tool for the wafer front and backside. The defect budget tables contained in the roadmap are based on a survey carried out five years ago. A new survey of semiconductor manufacturers is being conducted, and new defect budgets should be recalculated using updated data by the time of the next revision. The working group will survey semiconductor manufacturing companies for defect control limits of manufacturing equipment. In addition, discussions are currently taking place among the Yield Enhancement, Starting Materials and Surface Preparation working groups to move toward a unified defect/yield model, which will change some of the targets for the next revision.

For more information on yield management.