Photoresist Strip Faces Increasing Selectivity Challenges

It was about a decade ago that plasma ashing — a dry technique for stripping the photoresist after etch or implant processes — was really coming into its own, taking over most of the bulk resist removal from wet chemical removal methods, but also some residue removal as well.¹
 
When Gary Dailey, product manager, performance chemicals, at Mallinckrodt Baker (Phillipsburg, N.J.), started in the industry about 20 years ago, everything was wet, he said. For years, it was all wet stripping, but there was constant talk about going to all dry — to eliminate the expensive chemicals. The etch process improved, he noted, but it was still necessary to use some sort of wet chemical cleanup after every ashing process. Since then, the industry has continued to shift back and forth between wet and dry. "The aluminum era went from wet, then pushed toward more dry, and then copper jumped in and we saw a major shift back to wet. With the arrival of low-ks, the equipment people had a major challenge out there trying to develop processes and equipment that do not damage these very sensitive materials. And because of that, people have stuck with wet processes."

But the industry seems to be heading toward another reversal, trending away from years of dry processes. As features shrink further into the 65 and 45 nm regimes, there is growing concern about the amount of damage plasma processes could induce. "In spite of years of trends moving toward the Holy Grail, if you will, of an all-dry process, we're moving back toward an all-wet process because of the sensitivity of some of these materials, even to reductive ashing," said Michael Fury, vice president of R&D and engineering at DuPont EKC Technology (Danville, Calif.). "And so we're seeing a lot of request for an all-wet process that includes the photoresist bulk strip, the residue removal, the removal of any gap fill material that may be used in the damascene process, any ARC materials — in other words, all the transitory materials."

The RapidStrip 320 is a dual-chamber dry strip system for FEOL cleaning, including complete removal of heavily implanted photoresists. (Source: Axcelis)

Ideally, the chipmakers would like all of it removed in one step, Fury said, but that's a pretty tall order. Leo Archer, vice president of emerging technologies worldwide at SEZ (Villach, Austria), agreed. "The problem today is that that's quite difficult to do because resists and some of the low-k materials can be quite similar," he said. "And some of the ARC materials are also quite similar. So now you're asking to be selective between three materials that can be quite chemically and physically alike."

While cleaning companies might well cherish a resist chemistry optimized for removal, what's important to keep in mind is the resist's primary role — namely, to protect an underlayer from etch or ion implant processes. So it's unlikely that a resist could be optimized to achieve both a strong mask function and an easy stripping. In fact, far from getting easier, resist stripping is becoming increasingly complex, what with such material considerations as low-k and high-k dielectrics and ever more stringent requirements for zero substrate damage (Fig. 1 ).

"Even in some of the simpler structural steps in the device, you start imposing the requirement that you have zero silicon loss budget," Fury said. "Because some of the functional layers are so very thin that, through all these cleaning steps, you can't afford to lose even a single monolayer of silicon."

Damage control is particularly important as features get narrower — with gate stacks at the 45 nm node down to 25 nm wide after etching. "If we could etch a lot of material, there wouldn't be any issue of removing particles," said Jeffery Butterbaugh, chief technologist at FSI International (Chaska, Minn.). "But we can't etch very much, so now we've got to figure out how to provide physical energy to remove particles. And so it's that balance of providing enough physical force to remove particles during the cleaning process without damaging structures."

Even though there is growing interest in what wet cleaning can do with leading-edge devices, there remains a great diversity of resist stripping methods used, and it is by no means clear that the industry will go full tilt in one way or another. "I think we'd be foolish to think that it's going to go all one way and exclude one sector of the market," Dailey said.

1. The photoresist strip process faces several, often competing challenges, particularly with the introduction of new materials like low-k dielectrics. (Source: DuPont EKC)

While several companies work with various methods to use plasma processing to their advantage, wet cleaning is no slam-dunk. At the back end of line (BEOL), the major issue is dealing with low-k materials, which are susceptible to damage during the etching and ashing process. But the operating space for wet chemistry has shrunk considerably as well, Fury said. "We want grain environmental chemistry — we don't want to have waste disposal problems; we require compatibility with maybe six materials in a stack as opposed to only maybe two or three materials that were exposed in previous generations, so you've got that complexity; you want to remove the copper oxide, but you can't corrode the copper, and those two concepts are directly opposed to each other, chemically speaking; and you want to do it on a single-wafer tool, so you want it done in a one-minute process instead of a 30-minute batch process. And so the only way to get faster is to have a more aggressive chemistry when we've just gotten through saying that you want environmentally compatible chemistries. So the operating space that's available really has shrunk down quite a bit."

Until high-k dielectrics and metal gates actually come into play, the main issues still facing the front end of line (FEOL) are just mimimizing the amount of silicon that's lost in the source and drain area, Butterbaugh said.

"This becomes very critical especially when you look at SOI structures where you have very little substrate to lose, where actually the roadmap for 65 and 45 nm node technology calls for <0.4 Å stripped by wet chemical clean," said Harald Okorn-Schmidt, vice president of global research at SEZ. "When you count the plasma-damaged material, which is stripped also in the wet chemistry, it's just far, far beyond this target."

What's making things particularly difficult in the FEOL is the move to higher doses in ion implantation (Fig. 2 ). High-dose ion implantation creates a carbonized crust on the top of the wafer, with the physical and chemical properties of the crust varying depending on implant conditions, Okorn-Schmidt said. Very high-dose implanted resists are particularly difficult to remove. "What you can do in the front end of line is you try to create a very strong oxidizing environment where you can dissolve that off," he said. "The crust itself is very hard to dissolve, or at least very hard to dissolve in a very fast manner. But there is no reason that you can't over time dissolve this crust."

2. This example shows pre- and post-strip images of ion-implanted photoresists. The pink regions on the left show the resist, with the right-hand image showing just a ghost image of the implant pattern into the silicon surface. (Source: FSI International)

Higher implant doses call for more aggressive chemistries to remove the resist. At the same time, however, extremely shallow junction depths are calling for very high selectivity. "And generally those two things are mutually exclusive," said Ivan (Skip) Berry, director of technology at Axcelis Technologies (Beverly, Mass.).

Increased implant doses are a consequence of device scaling. "You want to keep the source/drain contact resistance low. But the junction has to be shallow to prevent short channel effects, so you need some resistance. You've got to improve resistivity of the source/drain, which means the doping levels go up for the source/drain implant. Then you have the extension implants, which also scale based on the channel dimensions, so those doses are going up now," Berry said. "It used to be an implant dose of 10¹⁵ was a high-dose implant. We're now seeing things approaching 10¹⁶ dose. In addition, people are doing pre-amorphization implants to get the junction shallower. So not only do you have the issue of the implanted dose going into the photoresist, you also have the pre-amorphization implant to deal with too."

As dosing levels rise, so does the silicon damage caused by the heavy ion bombardment. And there is growing concern about the use of plasma to strip the implanted resists because of the damage it can do. In the past, a typical process for stripping resists after high-dose implant was to do so in an oxygen plasma, following that up with a sulfuric peroxide clean, for example. But more and more, the plasma strip process is damaging the silicon, causing the sulfuric peroxide mixture to etch the damaged silicon away. "The junctions are so thin, you have very little amount of silicon budget you can actually consume," Berry said.

In fact, the International Technology Roadmap for Semiconductors (ITRS) calls for a silicon loss of <0.4 Å per cleaning step starting around the 65 nm node. "That number is something we don't have really good methods to even measure," Berry said. Also, the gate oxide is getting so thin that the clean after source/drain extension implant can't consume any of the gate oxide, he added.

Axcelis has been hinting about a possible solution for more than a year, but is not yet ready to show what it has up its sleeve. "If you look at the issues that you have to address with gaining selectivity, you have to prevent etching and oxidation of silicon. So you need a highly selective process. And most selective processes tend to be chemically driven rather than physically driven," Berry said. "Additionally, you tend to get higher selectivity at lower temperatures, but you also suffer from throughput when you go to lower temperature. So those are the things you have to trade off. If you're willing to take a long time, you can achieve the objective of clean wafers and high selectivity, but it may be a process that isn't manufacturable from a cost standpoint. We think we have a solution to that dilemma. And we will see how that progresses."

At the 65 nm node, the general feeling is that conventional processes will be able to get the job done, but it's not clear whether current solutions will be able to take the industry to 32 nm or beyond. "At 32, it's not clear. And beyond that, I think something new is going to be needed. Or at least there's an opportunity for something new at 32 and beyond," Berry said. "But you never want to discount the incumbent — how far can it be extended, etc. But it's getting harder."

FSI is finding that the best route for removing implanted resists is to just continue working on sulfuric-based processes, according to Butterbaugh. "We're focused on improving the sulfuric-based processes and their combination with the SC1 step — just kind of an overall optimization to get maximum removal capability with minimal material loss," he said. "It's really an issue of trying to get the process as hot as possible, and so there's a lot of different process sequencing and hardware development work that we're doing in that area."

Like some other cleaning companies, FSI is working to come up with an all-wet process that could strip the implanted resist. Although a sulfuric peroxide mixture could get the job done, there is some question about the critical throughput constraints. "We're trying to optimize the speed of the process so that we can get adequate throughput," Butterbaugh said. "Some people are working on this on single-wafer type tools, and our focus has been on the batch tools. And I think because of the length of the process, this type of all-wet resist stripping for implanted photoresists is probably going to have to be done in a batch tool because the cycle times are going to be too long in a single-wafer tool."

Meanwhile, the debate between dry or wet cleaning rages on. And it's certainly not always one or the other. "There's a large parameter space that can be explored between whether it's plasma heavy/wet clean light, or plasma light/wet clean heavy," Berry said. "And different companies are taking different approaches."

FSI, which is involved in post-ash wet cleaning processes, has been focused on developing new and optimizing current processes for that post-ash cleaning step that will minimize the amount of material loss. But the company has also started working on processes that could eliminate the need for ashing. "We've gotten a lot of pressure from the IC manufacturers to develop the capabilities to strip implanted photoresists because they see that it's actually a combination of the ash and clean process that is leading to material loss," Butterbaugh said. "The ashing process oxidizes the silicon surface or causes some surface damage, which then makes it etch faster in the cleaning process. So we've had several requests to look at eliminating as much ashing as possible to see if that can improve their material loss problems in the front end of the line." It is a similar situation in the back end of the line, he added.

SEZ is taking a hard line against plasma processes, contending they will have to go away completely because of the damage that plasma causes. "We have worked in the past with plasma companies to synergize the process between the dry and the wet as one alternative to solving this problem," Archer said. "But the customer is driving us more and more to eliminate the plasma completely."

An all-wet strip would eliminate the cross-linking that takes place in a plasma environment, making the polymers easier to remove, Archer said. "So now you can envision having a chemistry that will come in and remove whatever resist remains and whatever residues remain, hopefully in one step." Despite the time involved with an all-wet process, Okorn-Schmidt said he thinks a required throughput could be reached, especially considering that it's really competing with an ash step combined with a wet bench.

One problem with even a partial ash is that it can leave a lot of organic functionality on the surface of the wafer, so subsequent processing steps must use fairly aggressive organic-based solvents to try to get them off, Archer noted. "Now, in the front end of the line, very clearly there's always concern about just how many organics you have on the surfaces," he said. "But in the back end of the line, you have an added problem because, as you start to go to 45 nm, 32 nm and even below, you're going to be looking at materials that have more and more organic functionality. They're going to be more and more porous, and they're going to be more and more hydrophobic. And some of those materials are going to be very susceptible to attack from some of these solvents."

But several chipmakers that have worked with plasma ashing through the 65 nm node are trying to see if they can extend it down to 45 nm because it's something that they're comfortable with, according to Ben Cruz, applications engineer at Mallickrodt Baker. "A lot of their engineers are very familiar with the processes, and to do another capital investment on all-wet tools when you don't know much about it is a big leap that they have to take. And some companies probably aren't willing to do that." Each company has its own reasons for staying with a process or going to another, he added. "We have heard more people are jumping ship from ashing processes to an all wet process because of the sensitivity of the porous low-k dielectrics. Right now, it's hard to maintain that k value after ashing. But at the same time, with the all-wet strip process, we have to find chemistries that are not as strong or that won't affect the k value of that material as much as traditional solvents have done in the past."

The low-k dielectric is a significant issue in the BEOL. "Our biggest challenges are trying to find a chemistry that's compatible with the low-k dielectrics. They're so much more sensitive than traditional low-k or TEOS-type substrates that we've been working with," Cruz said. "It's become a real challenge to find something that's compatible with that, while also still being able to clean the resists off the wafer."

Trying to remove a carbon material from a carbon-containing dielectric film comes down again to selectivity. If the low-k material is exposed to an oxygen plasma, the carbon will be depleted from the low-k material, thereby raising its k value. According to Berry, there are multiple approaches that companies are taking to resolve this issue:

• Never expose the low-k dielectric to a plasma by using hard masks and conventional stripping.
• Never expose the low-k dielectric to a plasma by using all wet cleaning.
• Don't expose the low-k dielectric to a plasma, but rather heat it in a reactive hydrogen environment.
• Expose the low-k dielectric to a plasma, but only at very low temperature, and in a highly directional anisotropic approach using low-temperature oxygen RIE.
• Various combinations of the previous approaches.

"The industry still has not converged on a unique solution, and may never, based on different people's integration schemes and requirements," Berry said. Axcelis uses what is not a plasma approach per se, but rather a thermal decomposition process that occurs naturally in photoresists. Heating the photoresist in an activated hydrogen background prevents a C-C bond formation, enabling the resist to completely thermally decompose, Berry explained.

As the industry moves to ultralow-k materials, things will become even more challenging. "The porous materials have some other issues with pore sealing, so then you have to worry about subsequent processing," Butterbaugh said. "Like liquid processes are going to penetrate the pores."

The cleaning of porous low-k dielectrics is a particular focus for supercritical CO₂ (SCCO₂) efforts, Butterbaugh noted. But that has also been the reason for SCCO₂'s slow entry into the market — the fact that porous low-k materials are being pushed out further. Whether supercritical fluids will be needed for ultralow-k materials is still up for debate. "From our standpoint, we've developed processes on current standard equipment that we think can address the issues of porous low-k," he said. "But there are a few people that consider that, with porous low-k, they're going to need supercritical CO₂ processing."

Although care certainly needs to be taken when working around copper, issues with the material have largely been resolved. For example, to avoid oxidizing copper and increasing its resistivity, stripping processes should not expose copper to high-temperature oxygen or oxygen plasma, Berry noted. But, because low-k films also shouldn't be exposed to high-temperature oxygen, it probably won't be used except with integration schemes making use of dual hard masks.

Still, with so many different types of materials exposed, compatibility is an overriding concern, and that is certainly true with copper integration, Fury noted. "You've got these various etch stops and barrier materials," he said. "And one of the things that you see in a lot of the integration schemes for damascene is that some of the fabs don't etch that last barrier of usually nitride or oxynitride layer — expose the copper — until the very end of the damascene process, so after they've even done the rest of the resist stripping and residue removal. They're protecting the copper surface as long as they can."

Although covering the copper offers some flexibility in terms of what chemistry can be used to remove resists and ARC layers, it doesn't necessarily make it an easy process, Fury added. For customers who have the copper exposed during an all-wet strip, one requirement is that the copper oxide also be removed — any copper oxide that forms during the removal of that last barrier layer above the metal. This is important for good contact resistance in the subsequent step. "If it's a relatively thick copper oxide layer, just counting on a pre-deposition sputter clean to get rid of it isn't reliable enough," Fury said. "So you really want to bring it back to the bare metal with the wet process, and then, if any native oxide forms, at least it's more predictable and thinner than it might otherwise be."

But, for the most part, the industry got through the copper challenge several years ago, Dailey said. "Copper right now is not a big issue. It's the dielectrics — the porous low-ks — and now, in the front of the line, that's a whole big change; we never saw any metals in the front, so you could use process chemicals like Piranha to strip there. As soon as you put a metal there you can't do that anymore because it attacks the metal. You've got to be taking a look at a whole new cleaning technology, from a part of the process that they never had it."

However, metal in the front end is another question in itself. High-k dielectrics and metal gates — like porous low-k dielectrics — keep getting pushed further out. So it's not just a question of when, but what. There are so many different materials still being looked at that the high-k/metal gate arena is too much of an unknown for cleaning companies to really know what the issues will be. But the key will be selectivity — removing the photoresists without attacking the metal gates. "If metal gates and high-k really come, it's really an expansion of challenges in the whole field of cleaning," Okorn-Schmidt said.

But there is still so much unknown at this point. "Is the metal gate community going to go in the direction of dual metal gate processing, where you have two very different metals — one which is chemically very resistant, one which is chemically actually very prone to attack because of the work functions you need," Okorn-Schmidt said. "The physical work functions are a direct relationship to their electrochemical behavior, to their chemical resistance, which many people don't realize. So selectivity is going to be the big buzz word there too. How can you selectively clean off contamination or unwanted or not needed anymore layers without attacking these very chemically sensitive materials?"

And it's difficult for the cleaning companies to get their hands on future materials when those materials aren't yet decided, Archer pointed out. "What we thought might take place at 65 nm went to 45, and now more and more it's looking like it's 32 nm," he said. "So it's very difficult to ask customers for representative stacks to work on when they're not even certain themselves what they're going to use."

With the chipmakers looking at a lot of different integration schemes, the metal gates are probably the bigger unknown than the high-k material, Butterbaugh said.

"Everybody's trying a slightly different spin on what metal they're going to put down in the gate area. And so every time you change one of those atoms to something else, you've got a different game you're playing," Dailey said. "We would love for everybody to settle in on one kind of metal structure, and then we can go develop a product that works for 15, 20 customers. That would be wonderful. Unfortunately, that's not even close to reality."

The reality for cleaning solutions today is that they are highly customized. "It seems like a lot of companies are using different integration solutions for these next-generation products, so it's very difficult to come up with a universal product that works on just about everything," Cruz said. "The compatibility issues of the different ILDs or the processing parameters that these companies use — that's kind of made it very difficult for us to come up with a Holy Grail of cleaning solutions, especially for copper."

Although a broader solution might be desired, that's generally not possible, Fury agreed (Fig. 3 ). "If we look at the stack and look at the process conditions, our expectations will usually be confirmed that they're doing something different than the fab down the street," he said. "But once we find a solution to the particular cleaning problem that we're working on, we can in retrospect start to identify some commonalities, and it's bringing us closer to a broad solution. But I would say we're still not ready to declare anything like that."

3. Cleaning solutions must be customized to particular processes. Although the same cleaning chemistries and process conditions were used in both cases here, they showed good results with one etch process (left), but not with the other (right). (Source: DuPont EKC)

From the chemical supplier's perspective, solutions also need to be modified depending on the existing equipment in a given fab — such as whether a line is set up for single-wafer or batch processing. "They don't want to have to be changing out tool sets if they don't have to," Dailey said. "So if someone's moved to an all single-wafer process for cleaning, they'd like to stay with that, unless there's a real compelling reason not to, because it's a big investment to go back to a wet bench. So you have to take into consideration the kinds of tools that are being used in the cleaning process as well."

Collaboration between chipmakers, tool suppliers and chemistry developers could go a long way to producing more manageable solutions in a timely manner, Dailey said. "If everyone's out there developing their products for their own very specific purposes and not taking into consideration the processes upstream and downstream, then you get yourself into trouble, and that's when you start seeing delays in product development."