Assembly and Packaging Get Interesting Down the 'Road'

The 2005 International Technology Roadmap for Semiconductors (ITRS) was released last month, and its coverage of assembly and packaging technology is indicative of the ever-changing nature of semiconductor technology. In addition to the usual challenges of cost and materials, assembly and packaging are part of the grand challenges, such as design and power usage. Even the usual challenges are changing.

Design is a bottleneck step in product development, since it is a complex task whose complexity keeps growing. Codesign of the chip, package and board has been addressed in the roadmap before, but now it is a necessity. The power requirements for 90 nm designs and below are such that the IR voltage drops in the package must not only be accounted for, but must also be a part of the design optimization. Since the management of overall power consumption is one of the near-term grand challenges, it will likely force codesign to be done in earnest.

Another way in which assembly is melding with IC design is three-dimensional through-die interconnects. Its immediate value is that it addresses the limitations of global interconnects, which is a long-term grand challenge. If an IC were to be made as a stack of four 10 mm square die with through-die interconnection, rather than one 20 mm square die, the overall global interconnect length could be reduced. Through-die interconnects can provide short interconnections with low parasitics and short signal transit times for all system-in-package (SiP) applications, though its cost may not be comparable to flip-chip.

The ITRS mentions other novel interconnect schemes, such as RF, microwave and optical interconnection, as proposed solutions for the global interconnect problem. Each of these approaches can also be used to improve interconnection speed within an SiP, and promising work has been done toward that end.

Keeping packaging costs down has always been important. The industry is coming to a crossroads about the scaling of packaging cost. Right now, the package costs as much as the die, if not more, in many cases, and the cost of current packaging technologies will not scale as needed to meet ITRS targets. Keeping these costs under control is as much a design challenge as anything else. Minimalist innovations pop up from time to time, and they must continue to come.

One of the reasons that packaging costs are not on track to scale as desired is that less R&D work is done on packaging technologies. Margins are smaller on the back end, and this is the primary reason that less is spent on process development.

Wording in the executive summary of the ITRS document says that the industry will require more development work to be done, along with the suggestion that there should be enough money to be made from consumer electronics to pay for this development. If any of this is to occur, attitudes about the value provided by packaging services will have to change drastically in the positive direction.

As for the difficult technical challenges, the roadmap indicates that direct connection to copper pads is still important, along with materials and processes that do not impact the reliability of low-k dielectrics. The main concern here is not cracking the copper diffusion barriers, which can happen with wire bonding or the thermal stresses associated with flip-chip attach. Probing without affecting reliability will also be a challenge.

For wafer-level packaging, pad pitches as low as 150 µm with pin counts above 100 are the targets in the near term, along with the development of "compact" ESD structures.

With the recent increase in the use of ultrathin die, thinning and handling are considered challenges. When wafer thicknesses get below 100 µm, silicon becomes very flexible. This can be a good thing for the reliability of a chip after it is packaged, but it is a challenge to handle them. Some "singulation by thinning" methods have been developed, in which a partial depth cut or etch is done on the front side, and the wafer is thinned until those cuts are reached. This may be the best way to satisfy the challenge for singulating without degrading low-k reliability.

Long ago, passive devices were fabricated on the chip along with transistors, and these techniques are used now on silicon SiP substrates. Integrating passives and transistors would be too expensive now, but there has been talk in recent years about putting passives in the interconnect layers of the chip. This talk has finally worked its way into the ITRS. The thin-film technologies exist for embedding things like power-conditioning capacitors in the upper interconnect layers, and there may be enough capability in design tools to arrange for parasitic effects in the interconnect layers to give the desired effects. Making such choices presumes a codesign setting like the one the roadmap is calling for.

The long-standing desires for improved organic substrates, handling high currents and thermal management for hot spots are still there, along with the desire to keep reducing kerf losses and wire trace pitches.

The semiconductor manufacturing industry as a whole is on the verge of changes that could be described as mutation. Assembly and packaging technologies will mutate as a part of it. Not only will packaging technologies change, but the way packaging technology interacts with front-end technology will also have to go through some interesting changes.

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