Options Narrow at 45 nm

FinFETs won't be used. High-k and metal gates won't be used. Companies will not necessarily be using silicon-on-insulator (SOI) substrates. But the one technology that will be indispensable at the 45 nm node is strain engineering — and lots of it. The performance benefits afforded by mobility enhancement in the channel region of today's transistors is so great, relative to other performance levers, that the emphasis is increasingly put on this technology to improve chip performance. Because the oxynitride/polysilicon gates have reached their performance limit, process and material innovations have become the levers that enable transistor performance scaling to 45 nm and beyond. In addition to strained silicon, there are, of course, other significant modifications taking place on the chip — in shallow junction engineering, low resistivity contacts and multilayer interconnects — but for the 45 nm node, strain engineering is stealing the show.

At the recent IEDM, AMD (Dresden, Germany) talked about combining four stress techniques to improve NMOS and PMOS drive current — an approach that yielded an overall chip speed improvement of 40% relative to non-stressed devices with the same feature sizes (Fig. 1 ).¹

This article will cover the latest developments in strain engineering, the barriers that high-k and metal gates have yet to overcome, and the progress in multilevel interconnects and contact engineering for the 45 nm device generation.

At reduced gate lengths, the challenge is maintaining high drive currents (I_on) with acceptable leakage (I_off), while controlling short-channel effects. However, the industry is now at the scaling limit of oxynitride/polysilicon gates, where more shrinking will not boost performance because of leakage, power dissipation and tunneling effects through the thin gate oxide.

1. Four stress techniques — dual stress liners, stress memorization (SM) and an embedded SiGe S/D — were fully integrated on a partially depleted SOI substrate. (Source: IBM and AMD)

As a result, device manufacturers are turning to alternative materials (high-k/metal gates), band engineering methods (using strain) and alternative transistor structures, such as double gates and ultrathin-body SOI. Though significant progress has been made in high-k/metal gates, the alternative gate stacks are not expected to be implemented in manufacturing prior to the 32 nm node, if then. Likewise, 3-D devices such as finFETs will take a backseat to the continuation of planar CMOS approaches. With simultaneous work in all these areas, most IC manufacturers are finding that strain engineering delivers the greatest returns at this time, and it appears to be scalable into the foreseeable future. Table 1 shows a strain engineering and gate-stack roadmap for these transitions.

Transistor scaling, of course, has a negative effect on interconnects. For logic companies using multilayer copper interconnects, there are a few options to maintain the performance of scaled interconnects for the next several generations, such as the replacement of physical vapor deposition (PVD) with thin atomic layer deposition (ALD) barriers, which will be discussed.

Strain engineering involves straining of the silicon crystal to increase the mobility of charge carriers in the channel (electrons in NMOSFETs and holes in PMOSFETs). An added benefit is that it reduces the source/drain series resistance. Compressive strain is induced in PMOS transistors, typically using epitaxially grown SiGe source/drain and/or a compressively strained nitride layer over the gate. The greatest emphasis is given to the PMOSFET, since hole mobility is typically three orders of magnitude less than electron mobility. In NMOS transistors, a tensile strained nitride layer is used. These processes induce approaches that have proven to be the most manufacturable and cost-effective, and were first implemented in manufacturing at the 90 nm node.

Since electrons move faster through silicon with a (100) orientation and holes move faster through silicon with a (110) orientation (the orientation of most substrates), hybrid orientation technology (HOT) has developed to increase drive current as well. This approach, so far pursued mainly by IBM (East Fishkill, N.Y.), has resulted in 20% reduction in gate delays on bulk silicon.^2,3 Though this process may be limited by complexity and cost, engineers are working on simplifying the process and making it more manufacturable.

Another method that can be used is biaxial strain or global strain, where the entire wafer is strained by various methods. This approach is not likely to enter manufacturing until the 32 nm node or later because of defectivity and integration issues (Fig. 2 ). However, it is expected to complement process-induced (primarily uniaxial) approaches at some point.

2. At or beyond the 45 nm node, hybrid orientation technology and biaxial stress (global stress) are likely to join already implemented stress liners and embedded SiGe layers for strain engineering. To date, these technologies have been shown to be additive. (Source: R. Jammy, IBM/Sematech)

As mentioned previously, AMD, together with IBM and Toshiba (Tokyo), developed a third-generation strained silicon technology that combined dual stress liners, stress memorization in the NMOS, and embedded SiGe in the PMOS devices.¹ Figure 1 shows an illustration of the cross-sections of the devices with SEMs. The device was manufactured on partially depleted SOI using a 90 nm process and scaled to a 65 nm process. A novel integration scheme was used to embed SiGe very close to the gate. SiGe growth is prior to transistor implants. Tensile strain is memorized into the NMOS using poly implants and a stress transfer film that is annealed and removed. After nickel silicidation, the compressive liner was deposited and removed from the NMOS region; then the tensile liner was deposited and removed from the PMOS region. The researchers noted that resistance and poor surface mobility can significantly limit drive current improvements for a given stress-induced mobility improvement. Resistance must be reduced through NiSi process optimization, and attention to layout interactions is important between compressive and tensile liners, which exert biaxial stress.¹ PMOS and NMOS saturation drive current increased by 53% and 32%, respectively, leading to 40% higher product speed. Resistance reductions were imperative to gaining the full additive benefits of the stressors. Novel methods will be needed in the future to accommodate stress-induced mobility increases. Next-generation SiGe stress methods will employ higher germanium content and tighter spacing between the gate and S/D regions.

In another combination of dual stress liners and embedded SiGe, researchers from Toshiba and Sony (San Jose) explored the scalability of these approaches.⁴ They used simulation to examine stress in X and Y dimensions for dense transistor layouts. In these cases, channel stress in the X direction increases to its peak right before the space between the electrodes is filled; then it declines rapidly. Stress in the Y direction increases as thickness increases, even after the space is filled. Therefore, the optimal stress configuration is when the stress liner almost completely fills the space between dense transistors. Between device generations, if gate length is constant, channel strain decreases as gate spacing decreases. Stress decreases because the total volume of SiGe decreases as gate space decreases. However, both X and Y stresses stay the same with scaling because recess depth, sidewall and gate-height scaling compensate for the lack of gate-length scaling. For the 32 and 22 nm nodes, Toshiba and Sony modeled necessary stress levels assuming 70% scaling per generation. Generally, liner stress needs to be improved by 11% and 35% for the 32 and 22 nm nodes, respectively, to maintain performance.

The mobility roadmap in Figure 2 indicates that HOT, fully depleted SOI, novel materials and multigate FETs may be combined with uniaxial stress methods, as well as biaxial stress methods, as early as the 45 nm generation. However, it will be only the most cost-effective techniques that will be used, especially for low-power applications.

Significant progress has been made in the development of high-k dielectrics, especially hafnium silicates (HfSiON) and hafnium dioxide (HfO₂). The greatest hurdles have been dealing with the problem of Fermi-level pinning, which leads to higher threshold voltages, mobility degradation and general reliability issues.

In high-k, Fermi-level pinning is thought to be caused by gap states induced by Hf-Si bonds at the gate interface or by oxygen vacancies. A significant recent development has been the use of fluorine to passivate defective sites and reduce interface trap density. Fluorine can be introduced into the channel region by ion implantation or annealing in fluorine gas. The overall effect is to reduce interface charge density and charge trapping, thereby leading to better threshold stability and CV hysteresis. Several papers presented at IEDM last month addressed the use of fluorine in this application.^5-7 Researchers from Renesas (Hyogo, Japan) demonstrated an improvement in SRAM cell transistor variability with a HfSiON/polysilicon platform compared to a SiON/polysilicon platform at the 90 nm node.⁶

Full silicidation of polysilicon gates (FUSI), particularly using nickel, has become an attractive approach to integrating metallic gates into CMOS devices for low-power applications. Advantages include the compatibility with mainstream polysilicon front-end processing, nickel silicide's mid-gap work function and the possibility of work function tuning by ion implantation. In addition, since the silicidation takes place at a relatively low temperature, it can be performed after junction activation.

However, some of the challenges with FUSI processing include gaining full silicidation on all features and integrating FUSI with minimal impact to the CMOS process. But perhaps the greatest concern is scalability. If companies are going to make a high-k/metal gate change in manufacturing, perhaps a single change to high-k and dual-function metal gates is preferable to an intermediate change to oxynitride/FUSI (a single-generation solution) or high-k/FUSI, only to eventually change to high-k/metal gates.

Still, most leading companies are investigating FUSI approaches. Intel (Hillsboro, Ore.) recently determined that the performance gain from a NiSi FUSI process and strained silicon technology are fully additive. Researchers achieved record-high drive currents in 35 nm gate transistors (NMOS I_dsat=1.75 mA/µm, PMOS I_dsat=1.06 mA/µm at V_dd=1.2 V, I_off=100 nA/µm).⁸ In their paper, Pushkar Ranade and colleagues at Intel stated that the FUSI approach relies on precise process optimization. And "it should be noted that either incomplete or excessive NiSi formation can lead to significant parametric variation ... variation in V_t, which in turn can be misinterpreted as a change in the gate work function." Device reliability, a critical issue for FUSI devices, measured as NMOS TDDB (time-dependent dielectric breakdown) and PMOS NBTI (negative bias temperature instability) was comparable to the control wafers.⁸ In the FUSI process, it is desirable to set the p and n work functions independently, as you would in conventional CMOS. And, although it is possible to dope the polysilicon prior to silicidation, researchers from IMEC (Leuven, Belgium) demonstrated that different nickel silicide phases (NiSi for NMOS, nickel-rich silicides for PMOS) can be used to obtain appropriate P/NMOS work functions and threshold voltages.⁹ Work function tuning of the NMOSFET was accomplished using ytterbium (Yb) doping. Since silicides inherently have narrow linewidth effects, the key in this process is controlling the effective ratio of Ni:Si thickness across all linewidths. Silicon thickness on the PMOS devices was reduced using a selective poly etchback prior to gate silicidation. The continuous silicide is confined between the sidewall spacers. According to IMEC, the simplified two-step silicidation process solves process yield issues of nickel-rich silicides related to volume expansion, stress, filaments and voiding.⁹

Table 2 sums up the latest progress of high-k with poly, FUSI and dual-work function metals. As shown, work function tuning and threshold voltage control are issues for both FUSI and dual-work function approaches. There are also reliability, integration and tooling issues, but some of the fundamental physics problems, such as inferior mobility, and current density, have been overcome. However, dual-work function transistors (HfSiON/TiN NMOS,

HfSiON/TaCN/TiN PMOS) have been demonstrated. Though metal gates, especially dual-work function approaches, are unlikely to be used before the 32 nm node, most of the semiconductor community is confident that the engineering obstacles can be overcome.

The interconnect is a passive element in the circuit that can only take away performance, not add to it. With the scaling of transistors, the degradation of circuit performance by the interconnection network affects signal propagation delay, power dissipation and signal integrity.

Because of scaling, the additional layers of interconnect that result and the necessary introduction of low-k dielectrics have made maintaining interconnect performance and reliability ongoing challenges. Manufacturers have, generally, focused on minimizing the resistance of the contacts, optimizing the copper via and line conductivity, and gradually lowering the dielectric constant of the intermetal dielectrics.

Following the transition from aluminum to copper interconnects, there is limited room for improving the bulk resistivity of the wire, other than by alloying the copper with small amounts of metals, such as silver. But this approach has not proven to give superior properties to pure copper. The focus then becomes one of optimizing the copper/barrier stack, via a transition to ALD bottom and side barriers and an electroless top barrier, in order to maintain low effective resistivity and integrity while keeping barriers as thin as possible.¹⁰ Traditionally, the PVD TaN/Ta liner has been scaled with the copper line, consistently displacing ~16-18% of the interconnect volume.¹¹ This displacement could be reduced — and performance improved — by making a transition to much thinner ALD TaN/ALD ruthenium bilayer, assuming that the integration issues can be solved. The result would be the equivalent of a reduction in effective dielectric constant (k_eff) from 3.0 to 2.55, which would make the biggest difference at the global line levels.¹¹

However, to date, a suitable ALD TaN film has not been developed. Issues include adhesion and incorporation of undesirable elements from the ALD precursors. For now, PVD processes will continue to be enhanced to meet the scaling needs of 45 nm and beyond.

A transition to electroless top barrier is leaning toward a cobalt-based capping layer (CoWP), which is selectively deposited by electroless plating.¹² One of the challenges here is getting a completely selective deposition. The key performance advantages would be enhanced electromigration (by two orders of magnitude) and the ability to reduce the dielectric constant of the subsequently deposited dielectric, if the current nitride or SiC-based dielectric cap can be eliminated.¹¹ However, the latter has yet to be determined, and most industry professionals say that this dielectric cap is still needed.

Low-k dielectrics have been termed a moving target, since they must be appropriately integrated with the metallization scheme. Current-generation products (130 and 90 nm) use bulk dielectrics of k=2.5-2.8, primarily SiOC chemical vapor deposition (CVD) films. Though k=2.2-2.3 films appear to be feasible, it seems unlikely that the industry will be able to cost-effectively integrate materials with a bulk k value <2.0. The inability to integrate advanced porous low-k films is expected to drive numerous advances on the interconnect design side.¹⁰

Another primary concern with scaled interconnects is the so-called size effect: As the interconnect width approaches the mean free path of electrons in copper (39 nm), resistance rises rapidly because of electron scattering at the metal surface and grain boundaries. The industry has not found a "solution" to this problem. However, it appears that clever interconnect design solutions will come into play to minimize size effects.

Contact resistance represents another impending concern, which ramps rapidly at dimensions below 65 nm in diameter. Typically companies use titanium (PVD) for improved contact, a TiN barrier, followed by a tungsten nucleation layer and tungsten fill (all CVD). A switch to ALD for the liner and nucleation layers and a move to a lower-resistance tungsten with a smaller centerline seam could together provide up to 50% improvement in net resistance of conventional contacts. Long term, device manufacturers might possibly replace tungsten contacts with copper.¹¹