Executive Roundup: What 2006 Has in Store

Tom St. Dennis
Senior VP & GM, Etch & Front End Products Business Groups
Applied Materials

I am relatively optimistic for 2006. The global economy remains remarkably resilient, and the electronics market continues to show good growth driven primarily by mobility and price. Cell phones and consumer electronics items, such as next-generation game consoles, digital televisions and MP3 players, are expected to show strong growth. In light of this demand, the Semiconductor Industry Association (SIA) has steadily increased its chip sales growth forecast for 2005 from flat year-over-year in November 2004 to 6% in June 2005 and 6.8% in November 2005. SIA is forecasting a 2006 semiconductor sales growth of 7.9% driven by flash memory, DSPs, microprocessors and logic devices.

Recent results from the foundries and all fabs have shown utilization rates trending up, approaching full utilization, which should result in increased capital spending in 2006. This sets up the year to have a growth of 5-10% for the semiconductor capital spending and wafer fab equipment markets, with the equipment market growth somewhat ahead of the capital spending because of the increasing proportion of equipment expenditure.

During 2006, several technology trends will require attention to maintain industry and market momentum. Efforts to bridge the gap between design and process and manufacturing, called design-for-manufacturing (DFM), must continue to achieve acceptable yield and industry profitability. Integration progress on new transistor materials and designs to increase drive current, cut leakage and reduce power at near-atomic-scale dimensions is needed to keep improving performance while not increasing power consumption. The industry's top technologists are also working to solve the challenges of capacitance, resistance and integration throughout the complex interconnect layers that wire together tomorrow's logic and memory chips. And all of these advances can only be efficiently achieved if the industry cooperates and shares interdisciplinary research. But overall, I remain bullish on the industry's ability to find solutions to these issues and, coupled with what I see as higher levels of innovation, we should expect the industry to remain on a reasonable growth trajectory into the foreseeable future.

I no longer see the semiconductor materials and capital equipment sector as a cyclical high-growth industry, but rather as a cyclical technology industry with some high-growth pockets. We expect to see strong relative growth in certain advanced processes, such as CMP and photolithography, driven by advances in technology and the migration to smaller geometries and copper-based processes. At 65 nm and below, contamination control becomes even more critical.

While we expect to see modest growth in overall industry performance in 2006, we expect companies involved in the processes I mentioned to benefit disproportionately. The days of "a rising tide floats all boats" are gone. Today, being tied to the right process with the right tool provider at the right device manufacturer is the key to growth and sustained profitability. We should see more consolidation, especially in the materials and subsystems segment. It's not logical for these sectors to be so fragmented given the concentration among toolmakers and the device manufacturers.

Finally, we will see the trend toward more "customer intimacy" continue. Getting closer to customers wherever they are in the world, with outstanding global product support, is as essential to thriving in this industry as any technological advancement.

There has been a gradual but dramatic change in both chipmaking and failure analysis (FA) over the past five years. We have been driving to a commodity-based business at a steady pace — and this is now becoming more of a reality. Chipmakers have fewer ways to differentiate themselves in the marketplace.

Equipment manufacturers are finding themselves squeezed by contradicting business imperatives; they are servicing a more mature industry, but are still expected to supply leading-edge technology. This only intensifies what has always been a demanding business.

We see this playing out every day in FA and, to a degree, in electrical testing, but more emphatically in physical FA. In technology nodes down to 90 nm, the ability to analyze in physical FA has kept abreast of the needs. But as we approach the 45 nm node, the needs outpace the solutions and bottlenecks occur. A rule of thumb decrees that metrology and analysis must be enabled for an order of magnitude less than the design rule or node. It is, therefore, no surprise that the industry roadmap calls for automated and practical physical sample preparation and analysis almost to the atomic level. That's where your creativity and innovation as a supplier — your technology roadmap — makes you vital to your customer. If you can accomplish that, it becomes your differentiator.

In the past, customers were willing to pay a high premium if you had the best technological solution. They are much more selective now. You have to have technology, cost-effectiveness and a future roadmap. That's the sign of a maturing and, for us suppliers of enabling equipment, a more challenging industry.

With all indicators pointing to a market reprisal beginning sometime in 2006, semiconductor equipment firms are looking to three major trends that will shape the next upturn:

• Asia taking hold as the center of the chip industry
• 65 nm production moving into high volume
• 45 nm development activities gearing up

Since the last up cycle, Asia's chip market has matured, demanding suppliers' full attention. For suppliers to win in this market, it means pushing down costs with more productive and reliable tool platforms. The good news is that DFM strategies do work, giving us a navigable path to lowering costs for customers.

At the same time, suppliers cannot afford to relax R&D investments; the technology questions are too great. In the implant space, for example, device scaling and development of new transistor structures (such as vertical transistors) fundamentally change the implant landscape, calling for a fresh approach to implant technology development — one that is focused more on what's happening on the wafer and less on system architecture.

At 45 nm, this becomes even more apparent, especially as the industry looks to drive transistor speed improvements with materials advances. Expect to see SOI technologies eliciting important changes in implant requirements, porous low-k materials requiring new cleaning methods and strained silicon technologies demanding novel film-curing techniques.

So how can equipment suppliers spend less at a time when customer requirements demand more? The near-term solution lies in pushing the envelop through productivity, efficiency and continuing improvements to business models. The longer-term solution lies in industry consolidation and partnerships.

The end of 2004 saw some inventory burn off for several of our customers, which extended into the first quarter of 2005 and dampened some of the optimism for 2005. Despite this, we saw a steadily improving environment through the year, and we expect to end up with close to double-digit growth. For 2006, we expect to see this positive trend continue.

As a materials supplier, our time horizons are relatively short, but all of the initial indications are looking good for next year. Regionally, the United States may lag in some areas in terms of volume (especially as we continue to see such strong growth in Asia). However, we are encouraged to see several leading-edge U.S.-based fab announcements by all of the top U.S. IC companies, as well as investment in the United States by some foreign firms. This commitment to advanced technology in the United States will continue to drive the use of higher-value materials.

As many industry leaders have noted, there is no single "killer app" akin to the PC that will drive demand in the semiconductor market. In 2006, we will continue to see digital consumer applications drive our industry. We often have a Westernized view of who the consumers of these applications are: the members of the highest GDP nations. However, the rapid emergence of a stronger economic class in what we used to think of as Third World nations, notably China and India, is going to have a much more significant impact on our industry going forward. The cultures and needs of consumers in these populous markets are quite different and must be well understood. As suppliers, we must develop technology not only to add capability to products to address these emerging markets, but to also lower the cost of producing them.

I agree with the view of a number of economists who have predicted that the world economy will begin a strong upward move in late 2006. 2007 should actually be a peak year, and 2009 and 2010 recession years. The companies that successfully seek ways in 2006 to address not only the Western consumer market opportunities, but also develop low-cost products aimed at the emerging consumer markets in Asia, will be the most successful in the long run.

The semiconductor industry pace is now moving to a different drummer: the consumer. In 2004, the chip industry saw the crossover from PC-driven to consumer-driven.

The volatility and uncertainty within the industry always makes market forecasting difficult, especially with the added unknowns of being more closely linked to consumers. However, assuming global economies remain solid, our outlook for 2006 is positive. Fast-growing consumer markets will continue to drive the demand for semiconductor devices with expanding demand for cell phones (especially as consumers transition to 3G cell phones in the next few years), digital televisions, game consoles, notebooks, PCs and automotive electronics. We expect applications for NAND flash (used in products such as MP3 players and digital cameras and cell phones), which helped the memory segment to expand in what otherwise would have been a more tepid memory market in 2005, to continue to grow in 2006. Regionally, we expect that the majority of semiconductor equipment expansion will be in Asia, with emerging markets such as China continuing to grow.

Consumers want products with high performance, compatibility and mobility at lower prices and power. To achieve further improvements in performance and power consumption, semiconductor manufacturers must develop process technologies that can move 65 nm into volume production and demonstrate capabilities to 45 nm. With increasing R&D complexity and costs, we will see the formation of more strategic alliances and partnerships, where IC companies leverage manufacturing technology, assets, experience and scale to shorten new product development time, lower manufacturing cost and accelerate time-to-market.

During the transition to the digital consumer era, the semiconductor equipment industry must continue to build business models that will enable companies to exit this decade with positive retained earnings and positive cash flow — something the industry as a whole has never done before.

During the past 12 months, a record amount of 300 mm automated material handling systems (AMHS) have been installed in customer fabs. This is in contrast to the shipment trend for other front-end equipment, which was generally flat to down for most of 2005. This is significant because AMHS capacity typically needs to go in ahead of process equipment. Assuming that there are no changes in these customers' views of future demand, we would expect tool shipments to begin to ramp in early 2006 to "fill in" capacity underneath this AMHS.

We also are encouraged by the proliferation of new end-market products that emphasize mobility, low power consumption and long battery life, and that are creating a seemingly insatiable demand for flash memory. The many applications of flash may, in the aggregate, represent the "killer application" that will accelerate demand for incremental capacity in the near term.

The display market emerged as one of the electronics manufacturing industry's fastest-growing segments in 2005. For example, shipments of TFT-LCD panels used in TV sets topped 20 million last year, compared with 12 million in 2004, according to an estimate by DisplaySearch, as capacity ramp and price cutting by OEMs fueled demand. Shipments of displays for a variety of applications are expected to grow by double digits this year as well.

Asian companies account for more or less the entire display production. At the same time, we see a fast shift of photomask-related business for semiconductors toward Asia. Vendors of photomasks and the tools that make all types of photomasks, and other key suppliers, will continue to build their presence in Asia. In particular, this expansion will occur in countries such as Japan, South Korea and Taiwan in 2006 and beyond, as these countries are growing faster than China.

Equipment suppliers for semiconductors may experience a period of stable growth — and a respite from cyclicality — because buyers are fewer and larger, and sales will be driven by the steady evolution to tighter design rules rather than the introduction of dramatically new applications. This is good news for our semiconductor customers. However, the display industry will encounter greater volatility, as it's driven by consumer demands fueled by price erosions, mega events and technology shifts to HDTV and digital broadcasting.

The ongoing consolidation among equipment suppliers will continue. This consolidation ultimately will be a factor supporting price stability for the remaining suppliers, because it will lessen pressure to engage in unwise price discounting that ultimately harms the industry.

In high-end microprocessor markets, technology metrics are shifting from gigahertz to performance per watt, while the economic metrics are shifting from materials cost to total cost. The question with respect to SOI then ceases to be, "Should I or shouldn't I?" and becomes, "How can I afford not to?" Witness the new generation of SOI-based game consoles, which are expected to ship by the millions every month.

Those focusing on 45 nm technology choices this year will be looking at ultrathin SOI and mobility-enhancing strained SOI in complement to local strain techniques. The most aggressive IC players are investigating finFETs for the 32 nm node. Engineered substrates will also be leveraged as key enablers in system-on-a-chip for low-power, portable RF applications.

We'll hear more from companies leveraging fully depleted SOI for ultralow-power applications that run on small but ubiquitous energy sources, such as body heat and natural illumination. At the other end of the scale, SOI bipolar processes for high-voltage, analog and smart power applications will continue to gain ground, as will applications in photonics and MEMS.

The combination of these factors indicates a fast ramp for SOI device manufacturing in 2006.

In the past 10 years, capital expenditures for process control have doubled as a percentage of total equipment investment. Metrology's growing impact on productivity — and pervasiveness throughout the fab — is certain to continue in 2006 and beyond. Not only are more wafers being measured than ever before, but there are also more measurements being taken per wafer. Every facet — film thickness, uniformity, critical dimensions, etc. — of each wafer (not just statistical samples) must be closely monitored and tightly controlled.

Shrinking process windows raise another metrology challenge. Uniformity mapping for today's high-value 300 mm wafers require metrology at as many as 49 sites, compared with as few as five site measurements on smaller wafers. To obtain tighter control while maintaining throughput and yield, the semiconductor industry is increasingly relying on integrated metrology (IM) over traditional standalone metrology. IM lowers manufacturing risk at a reduced cost; it eliminates bottlenecks inherent in standalone metrology while keeping a relentless watch on the process window. By enabling concurrent wafer processing and measurement, thus eliminating the transit time to and from an offline metrology tool, IM can achieve 10-15% higher throughput than standalone metrology.

As minimum feature sizes drop below 65 nm, an important trend in device manufacturing materials begins to take shape. Put simply, the need for silicon-based materials is growing like never before as the industry pursues a number of key technologies that rely on the development of new materials.

At the 45 nm technology node, for example, traditional TEOS-based HDPCVD and SACVD gap-fill technologies start having difficulty filling very narrow, high-aspect-ratio gaps found in shallow trench isolation and premetal dielectric structures. Recent developments indicate that novel silicon-based materials can improve the CVD process to achieve better gap fill, possibly extending the life of CVD technology for this application. Spin-on silicon-based dielectric materials may also be the answer to the extreme gap fill challenges of advanced technology nodes.

In the lithography space, we see silicon-based materials addressing challenges that organics may no longer be able to handle. In advanced technology nodes, organic materials need to be combined with silicon-based hard mask and antireflective layers to provide both the necessary etch resistance and lithographic performance required for the 65 nm technology node and below. Use of a silicon imaging layer in place of an organic resist can simplify the process even further.

These are just two examples, but the industry will continue to call for silicon-based technology to help address critical performance requirements, especially in the areas of high-k dielectrics, second-generation low-k dielectrics, selective epitaxial-deposited thin films and low-temperature silicon nitride.

Price pressures are dominating the electronics supply chain. PC vendors are selling $500 laptops. Sales of MP3 players are expected to pass 50 million units this year, but prices are stable or dropping even as onboard flash memory climbs from 1 GB (the maximum available in 2004 players) to 8 GB next year, according to market researcher IDC.

Consumers' expectation, of course, is that benefits will increase while costs decline. That marketplace reality, combined with increasing intolerance for errors on 90 and 65 nm wafers, has dramatically raised the pressure on fabs to control costs and extend efficiencies while also improving process performance. Gartner Dataquest estimates the value of a processed 300 mm wafer at $40,000 or more. A million dollars worth of wafers can be misprocessed in a few minutes, with huge cost and time-to-market implications. Consequently, IDMs, foundry operators and their tool suppliers have moved advanced process control — and, in particular, fault detection and classification (FDC) — from the "optional" category to "must have."

Indeed, FDC has evolved from an offline, backward-looking process to real-time pattern recognition and data analysis, based on a library of known faults. This approach maximizes equipment productivity and lowers equipment cost of ownership and wafer loss, while meeting market expectations for better, faster and cheaper products. Its increased implementation will be one of the good news stories in 2006 and beyond.

IC reliability, as the semiconductor industry moves through the 45 nm node, will be shaped by a number of economic and technology drivers.

For starters, performance gains at future technology nodes will largely come from the introduction of new materials that are often electrically unstable and/or unpredictable. This drives the need for a larger volume of reliability testing and at more points in the development cycle, including increased reliability testing in materials R&D and process development. The results will be more difficult to analyze because of the physics of the new materials.

In addition to materials science issues, device voltage scaling driven by low-power mobile devices will pose additional challenges. The ability of even the well-behaved Si/SiO₂/polysilicon/Al materials systems to deliver stable DC operation points like threshold voltage over extended product lifetimes is becoming more difficult. New electrically unstable materials systems will only compound the problem.

Finally, there is a lack of skilled scientists who can develop new materials systems, expand reliability test methodologies, and interpret the data from these tests to drive to robust, high-volume solutions. Consequently, the industry will need to rely on test suppliers not just for instrumentation but also for physics and materials science expertise.

Certainly one of the most significant issues faced by the semiconductor industry is the approaching transition from SEM to TEM as the core technology for many inspection and metrology processes. SEM has been the primary technique since we passed beyond the resolution capabilities of optical systems. Usable SEM resolution is generally in the range of a few nanometers, and is limited not so much by electron optics as by the spreading of the beam within the sample. In practical terms, this limits its application for metrology and inspection to features larger than a few tens of nanometers — a criterion already exceeded by many advanced processes.

TEM and (S)TEM can provide sub-angstrom resolution, arguably sufficient to carry us into the regime of molecular- and atomic-scale devices that are currently little more than ambitious concepts. However, acceptance of (S)TEM has been impeded by two areas of difficulty: the interpretation of high-resolution images and the preparation of samples thin enough to transmit electrons. Fortunately, recent developments in both areas promise a renaissance in (S)TEM use. Aberration correction has eliminated the effects of spherical aberration, bringing directly interpretable image resolution down to the 0.7 Å information limit of high-resolution TEM. Automated focused ion beam (FIB) techniques can reduce the time and cost of sample preparation to a level comparable to SEM. With continued development, we expect to see a dramatic increase in the adoption of (S)TEM for routine inspection and metrology.

Consumer requirements — small form factor, long battery life, wireless connectivity and data bandwidth — are driving many of the most challenging technology advancements in electronics design today. However, consumers have little understanding — and even less interest — in the incredible complexities associated with the design and creation of the ICs that deliver those performance characteristics. They just know that they want it faster, smaller and sleeker, and that they want it today or sooner.

The electronics industry needs to remove the obstacles that threaten the timely design, manufacture and reliability of these increasingly complex high-performance digital and analog mixed-signal ICs. To ensure acceptable yields at reasonable costs, manufacturability must be a key focus for engineers very early in the design cycle. Designers will need to have tools and methodologies available during design and verification that understand yield, reliability and performance risk factors, and that are able to address them whether they occur during design or manufacture.

Functional verification is an increasingly important "choke point" in IC and systems design, and will play an increasingly important role in the coming year for good reason. Consider the auto industry: With electronics now monitoring and controlling key safety systems in most motor vehicles, one undetected error during design could result in multiple product recalls or, worse still, compromised driver and passenger safety.

As an industry, EDA must provide product solutions that drive design productivity and manufacturing yield. As for the global electronics industry in 2006, innovation will continue to be the key.

Over the past year, we have seen a number of industry trends that I believe will continue to escalate in 2006. The overarching requirement is continued cost-effective innovation, the focus of which is enabling companies to optimize their core business and technological strengths.

Asia remains a driving force in the purchase of manufacturing tools. This includes Korea, Taiwan, Japan and fast-growing China. Suppliers must continually find innovative ways to remain competitive while meeting customers' technology requirements in a cost-effective manner. One key approach — another important trend — is cultivating and maintaining customer-intimate relationships, in which the supplier and customer work together so closely that they are virtually one organization, jointly pursuing mutual success. We view such close collaborations as a critical component of meeting customers' immediate and near-future requirements. Moreover, knowing what to focus on enables targeted R&D investment in potentially disruptive technologies.

Cross-vendor collaboration is also essential to meeting customers' needs, qualifying and ensuring interoperability with each other's tools to facilitate customer acceptance. Leveraging R&D efforts into a strong intellectual property portfolio is also becoming increasingly critical. This requires encouraging technologists to patent their inventions.

Historically, EDA technologies have played a major role in sustaining the productivity and even the viability of chip design. The challenges are increasing — industry analysts predict that by 2010 mainstream designs will most likely include geometries of 32 nm with 100 billion transistors on a die, as well as designs encompassing multichip systems. As the semiconductor industry moves further into the nanometer era, with feature sizes smaller than the wavelength of light used to create them, yields are falling with each generation. Solving this problem will require closer partnerships between design and manufacturing to create an integrated process whereby more of the manufacturing data is brought forward to be taken into account in the design phase; tighter integration of DFM and design-for-test (DFT) flows as the gap narrows between manufacturing and design; and new technologies that enable designers to factor in manufacturing and yield issues at each stage of the design, verification, tapeout and test process.

Use of DFM tools has already resulted in significant cost savings in terms of yield enhancements and reduced capital equipment requirements. The drive toward DFM will ultimately lead to an integrated back-end platform incorporating technologies that allow the designer to anticipate the effect on chip layout of the subsequent resolution enhancement features, as well as automated evaluation and yield enhancement of designs. Resolution enhancement techniques (RETs) have been the first technology to help close the gap between design and manufacturing, and provides a software solution to alleviate the subwavelength crisis. Other technologies are following suit, such as statistical yield analysis that enables designs to be modified to improve yields and reduce guardbands.

One of the most exciting industry stories for 2006 will be in the core of the transistor evolution: in epitaxy, tools and process technologies involving ALD, PEALD and high-k dielectrics. The underlying market potential for these technologies is tremendous, especially as it extends beyond semiconductors. By 2009, VLSI estimates the epitaxy market could exceed $500M, while the market for ALD could reach $1B. ALD for the broader applications' market could be 4× that.

If we look at applications for high-k dielectric films in development by IC makers last year, low-standby-power and high-performance logic devices, capacitor dielectrics for DRAM and flash memories, barriers for FeRAM, RF linear and decoupling capacitors, and metal films for gate and capacitor electronics — that impressive list is likely to grow in 2006, and for 65 nm and below. More significantly, I believe 2006 will see the first migration of high-k programs beyond R&D into production environments.

Advances in epitaxy will continue to expand that market as the materials evolution takes hold, and engineered substrates, such as strained silicon, SOI and strained silicon on SOI, and local stressors, such as SiGe, are further integrated into device designs. In 2005, we saw the first strained silicon 65 nm high-volume ramp, with more likely to follow in 2006; at the same time, developments in 45 nm will benefit from 65 nm integration success.

2006 is bound to bring challenges, as historically predictable cycles become less so, and macro economic pressures limit visibility and encourage caution. Ironically, it's those same challenges that drive innovation to more and more efficient levels.