Fixing Pattern-Related Defects Before They Hit the Wafer

Before making any mask, it is important to verify that there are no design-related defects and that there is a reasonable process window for manufacturing. These are two of the goals of design-for-manufacturing (DFM). A new hardware and software solution, DesignScan, from KLA-Tencor (San Jose) analyzes how each feature will print on the wafer by combining design with reticle transformation, aerial image and resist simulations. "Our image computer, defect detection algorithms, and simulation models have been optimized over the last 20 years. The primary engineering effort has been the integration and calibration methodology needed to produce highly accurate process window simulation within a time period that is acceptable in manufacturing," said Bill Volk of KLA-Tencor. For a 90 nm half-pitch design, the inspection routine typically takes 2.5 hours to analyze across nine focus/exposure conditions for an 8 × 8 mm (wafer-scale) chip.

"We do a full chip-resist image process window simulation on every feature, we inspect everything on that device at the litho conditions and at every focus and exposure condition that the user specifies," Volk said. "This can be used for the first two or three years of your ramp, making sure you don't have any yield surprises because there was a layout rule that was violated, or a feature that did not allow the OPC engine to properly apply OPC or a post-OPC data fracturing error. So the purpose is faster time-to-market at the target design performance through optimizing the litho process window."

Yung Feng Cheng and colleagues at UMC (Tainan, Taiwan) reported on the use of DesignScan at the recent BACUS meeting. The program uses identified performance and yield detracting patterns to reoptimize the OPC recipes through the focus and exposure matrix prior to reticle fabrication (Figure ). UMC also identified a new application for DesignScan: determining reticle CD target specifications using process window simulation across a range of target CDs. This is determined by biasing the post-OPC data by a few nanometers in both directions.

If there are defects found within the process window, the OPC recipe can be altered to fix the defects or the process can be re-centered for the design until no defects are detected in the process window. The program can be run outside the process window to improve the accuracy inside the process window or to look for hot spots — spots that might be monitored in reticle or wafer inspection.

A typical inspection is a two-step process. First, the best focus and exposure inspection is performed (simulated to the GDSII database) by simulating resist images at the best focus and exposure conditions and comparing them to the pre-OPC design database (GDSII) to detect possible defects caused by OPC decoration; second, the process window inspection is performed. Using the best focus and exposure condition resist images as the reference (F₀ E₀), each simulation within the process window is compared to the one at nominal conditions to detect any unacceptable variation in pattern fidelity. The defect detection algorithm checks for topographical change between a test resist profile and the reference resist profile. The defects it checks for include bridges, breaks, extra and missing printed features, CD variation defects, line-end shortening and interlayer overlap defects. The system uses a proprietary binning model to reduce the number of defect types. DesignScan binning injects lithographic hierarchy by grouping lithographically identical patterns together. The defects can be sorted by process window impact so that process window limiting defects can be reviewed first.

Once the inspection is completed, if no defects were found within the process window, the design is typically sent to mask tape-out. However, if defects were found, several courses of action are possible: The RET can be modified to fix the defects, or the process can be re-centered for the design until no defects exist in the process window. Once the design is "clean," running DesignScan outside the process window allows identification of hot spots in the chip, which can be locally fixed to extend the process window further, or hot-spot information can be passed to reticle and wafer inspection tools as places to monitor because they will be the first sites to fail if there is a process shift.

As opposed to typical verification software, the program uses physics-based models, which are easier to decouple, if needed, but also provide higher accuracy. "We don't have to do single-point calibrations, and instead we do a full Bossung chart calibration, which is more accurate," Volk said.

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