Carlos Mazure, CTO, Soitec

Carlos Mazure (Source: Soitec)

Carlos Mazure has managed Soitec's advanced technology development organization since 2001. He drives the identification and development of next-generation engineered substrates for the semiconductor industry, as well as the emerging applications effort, defining future business directions. Prior to joining Soitec, he was the director of business development at Infineon Technologies AG, and was involved with the IBM/Infineon DRAM development alliance. His experience includes work on SOI and BiCMOS high-performance devices and technology development at Motorola. Mazure holds two doctorates in physics, one from the University of Grenoble, France, and the second from the Technical University of Munich, Germany. He has authored more than 150 technical papers and holds more than 70 patents worldwide. Soitec (Grenoble, France) works with a proprietary layer-transfer technology that consists of a hydrogen-induced layer splitting bonded and transferred onto a handle substrate. It's a combination of layers and substrates of different materials used to create an optimized new substrate tailored to the requirements of the applications.

SI: With everything that has changed in our industry, what do you see as the CTO's main purpose today?

Mazure: Purely from the perspective of my position in Soitec, I wear several hats. In the operations area, we deal with new products — engineered substrates. This means close contact with customers, because if they don't have a chance to consider a certain substrate early in its development, they cannot develop their roadmaps ahead of time. This puts me in a position where I am also doing pilot-line development to enable our customers to be able to improve their own designs and device architectures as we introduce these value-added substrates.

SI: So you see your role as that of an advisor to your customers?

Mazure: That is the more classical CTO role, the operational one. I also guesstimate the direction of the technology and industry and define strategy so that we can plan accordingly and meet their needs.

SI: What is the center of your R&D effort's orbit?

Mazure: It centers in determining, from an engineered substrate perspective, what the microelectronics industry will need at least five years before it goes into production. This means I must focus on the correct choices, with little loss of time, very early on. If you look at the ITRS, the industry goes into a new technology node every three years, with the more aggressive companies doing so every two years. We must move faster than all of them, because the substrate is the first link of the chain. If the substrate isn't there, devices cannot be developed. This requires that we be extremely aggressive and willing to take risks.

SI: What does your technology roadmap look like for the next three years or so?

Mazure: Today, we have SOI in production, and it addresses several nodes. It's now in use at 90 nm, and we'll continue to respond to future technology requirements. We're already working or looking at 65 and 45 nm technology nodes. We realize that silicon, as such, is running out of steam for some applications. People talk about strained silicon in just about any conference one attends. The strain induced by layer deposition has limitations linked to chip geometry, gate pitch, etc.

Here is where strained silicon coming from the substrate — strained SOI — will give device performance an extra boost. It will be adopted at the late 65 nm node by the most aggressive designers, and by the rest at 45 nm. We'll see a trend toward more engineered substrates, where device architecture will build solutions on the substrate that best addresses device performance requirements.

SI: SOI is obviously becoming necessary for high-end chips, but you're dealing with a wafer that is almost 400% costlier than a regular silicon one. IBM has adopted it, Intel hasn't. What needs to be done to mainstream SOI?

Mazure: Cost is often mentioned as the reason to avoid SOI, but I don't believe that it is the real gating factor. We have early adopters, such as IBM and AMD, who not only have acquired considerable knowledge about the material, but particularly of how to design using it. So it isn't really about the cost factor, but rather whether the device maker thinks he is getting the full advantage that the material offers. The decision takes place at the design and integration levels, and is ultimately based on the IC product's performance.

SI: So companies that do not use SOI haven't, as yet, developed the necessary expertise to do designs that work best on it?

Mazure: Design, not so much wafer cost, is definitely one of the major points.

SI: Would it be fair to say this holds true for all engineered advanced substrates?

Mazure: Yes, I believe so. There are a number of companies driving the development of tools that will fully unlock the advantages of SOI for design engineers. This will be useful not only to newcomers, but to fabless companies. It will open a plethora of possibilities for RF applications, for example. Then there is the one-transistor DRAM cell, based on SOI, whose theoretical value can go below 4f², where f is the minimum feature size. The correct application of the material will solve many challenges that are currently viewed as problems. If you do a back-of-the-envelope calculation, you'll end up with the unusual situation where the SOI approach — if this type of memory is adopted — can be 40-50% cheaper than the bulk silicon approach. This is because today's microprocessors, high-end logic, etc., have between 50% and 70% on-chip memory — mainly embedded SRAM before the L1 and L2 cache. The L2 cache takes up a lot of chip real estate, and if you can reduce the embedded SRAM by a factor of 10, by moving from the transistor to the one-transistor cell, you gain a factor of 10. That also means you increase the number of chips per wafer or can add more memory and an L3 cache. So if you factor all this, SOI then becomes extremely competitive.

SI: Will silicon ever run out of steam?

Mazure: (Smiling) When I began my career in silicon, it was a fact of physics that 1 µm was the minimum limit for features. Since then, we've bridged several uncrossable limits, such as 1 Mb DRAMs being the maximum achievable integration density, X-ray lithography has to be brought online because otherwise smaller dimensions cannot be achieved, and so forth. Bulk silicon definitely faces challenges that will be difficult to overcome at 65 nm and further nodes. We believe that, with SOI and other engineered substrates, we can provide solutions to continue Moore's Law that will ensure the future of silicon for the semiconductor industry for many more generations. We are working daily with our customers on this with, for example, strained silicon on insulator, which is a good 45 nm node candidate.