5 nm Silicon Nanowire Transistors

Samsung researchers have demonstrated what could be the future of transistor technology: MOSFETs consisting of two 10 nm diameter silicon nanowires with a wraparound gate. The transistors exhibited outstanding off-state performance and were made on a bulk silicon wafer with existing lithography equipment, using a self-aligned dual-damascene approach. Drive currents were 2.64 mA/µm (n-channel) and 1.11 mA/µm (p-channel), and the on/off ratio was as high as 10⁸ . The work is scheduled to be presented at this month's International Electron Devices Meeting (IEDM), to be held Dec. 5-7 in Washington, D.C.

This year's IEDM has two sessions devoted to these new technologies:

• Session 11 — Solid-State and Nanoelectronic Devices: Nanotubes and Nanowires for Thermal and Electrical Applications
• Session 21 — Modeling and Simulation of Nanowires and Nanotubes

Semiconductor nanowires and carbon nanotubes are attractive building blocks because they can be synthesized in single-crystalline form with precisely controlled diameter, length and chemical composition. Nanowires offer potential advantages over bulk material systems, particularly enhanced mobility.

Similarly, metallic carbon nanotubes (CNTs), with their excellent thermal and mechanical properties, have been suggested for use as interconnects because of their high current-carrying capacity. This could help alleviate electromigration problems.

To fabricate what they have dubbed the twin silicon nanowire field-effect transistor (TSNWFET), the Samsung researchers began with shallow trench isolation (STI) etching and a trimmed SiN hard mask. Then, high-density plasma (HDP) oxide was filled into the trench region to form the STI. For using a damascene-gate process, SiN or an oxide dummy layer was deposited. After a damascene-gate photo process, the dummy gate layer between photoresist layers was removed, and the hard mask SiN layer was stripped. The active silicon layer was then partially exposed. By using the oxide dummy layer as a hard mask, the exposed silicon was trenched. After that, field oxide was recessed until the SiGe layer was exposed. Finally, the exposed SiGe layer was removed by a newly developed etchant that could selectively etch the SiGe layer against the silicon layer with the ratio of 100:1. Optionally, an additional H₂ anneal process was applied to get a circular cross-sectional shape of the nanowires. The Figures are top-view and cross-sectional SEM images showing the nanowire diameter smaller than 10 nm.

The SEM images above show the 10 nm nanowires. At left is a top-down view after SiGe removal, while the two at right show cross-sections.

In order to evaluate the intrinsic transport characteristics of a nanowire, no channel ion implantation was performed to avoid dopant fluctuation caused by the variation of impurity number and position in the nanowire.

In other nanowire work to be presented at IEDM, Purdue University researchers will describe their investigation of band structure and orientation effects in ballistic silicon and germanium nanowire FETs. They note that, in nanostructures, the bulk crystal symmetry is not preserved, so the atomistic band structure will affect both ballistic transport and scattering in nanotransistors. They will show that the ballistic performance of SiGe nanowire FETs has a strong dependence on wire orientation. Wire diameter also plays a key role: An interesting finding was that p-type nanowire FETs display increasing performance with a decreasing wire diameter for all cases, while the dependence of n-type nanowire FET performance on wire diameter is sensitive to the material type and wire orientation.

In addition, researchers from the University of Glasgow and the Laboratoire Matériaux et Microélectronique in France have studied ballistic transport in silicon, germanium and GaAs nanowire MOSFETs. They studied the influence of various channel materials and crystallographic orientations on the performance of nanowire MOSFETs operating in the pure ballistic regime using 3-D quantum mechanical simulations.

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