Process Control Investments Support Technology, Cut Costs

As IC manufacturing processes have grown complex, so have the hardware and software tools that monitor them. Techniques previously dismissed as expensive research toys, like spectroscopic ellipsometry, are routinely used for thin-film metrology. Neural networks, multivariate statistics packages, and automatic classification schemes augment the spreadsheets formerly used to manage process data. Once engineers identify yield issues and potential process improvements, run-to-run control, recipe feedback and feed forward, and similar software tools can implement and monitor desired process changes.
 
This arsenal of process metrology, analysis, and control hardware and software represents a growing fraction of total fab cost, while playing an increasingly important role in the fab's success. Though essential to prevent continued processing of scrap wafers, metrology and inspection were once viewed as a "tax" on productivity — a drain of time and resources that ideally should be redirected elsewhere. Since then, process control tools have become more powerful, while the process has become more complex, more difficult to control, and more expensive. Now, process control is as essential to the fab's success as is lithography or contamination control. Good process control practices achieve significant cost and yield advantages.

As used here, "process control" includes all methods used by the fab to collect process information, analyze the information, and act based on its analysis.

It includes metrology and inspection, statistical data analysis and process modeling, as well as "advanced" process control (APC) methods like run-to-run and feedback/feed-forward control.

Such a broad definition is important because data collection, data interpretation, and process intervention must work together. Without good data about what the process is doing, it is impossible to determine what needs changing. Without good analysis tools and algorithms, it is difficult or impossible to take a systematic approach to problem resolution. Without the ability to influence the process in real time, analysis may show what happens but is powerless to affect the outcome.

A broad definition of process control is also important as fabs plan investments. To achieve optimum results, sufficient resources must be provided for all three components.

Process control begins with data. Data about the wafer state shows when a problem exists; data about the tool and process suggests how to fix it. Finally, data shows whether a particular intervention was successful. As process interactions become more complex, it is important to consider the data generated by the fab — from incoming wafer inspection to final electrical test — as an integrated whole. The outcome of a copper polishing step, for example, depends on the oxide etch, barrier deposition, seed deposition, and copper fill steps preceding it. Fabs need software tools and data formats that can combine information from multiple sources.

Wafer metrology — the measurement of films and structures on the wafer — is a common and powerful data source. It can serve as a proxy for electrical test, identifying uniformity variations, defective vias, and other failures well before end of line. The stringent requirements of advanced processes drive the capabilities of new wafer metrology systems. James Dougan, principal staff engineer at Freescale Semiconductor (Austin, Texas), observed that smaller features require smaller measurement spots. Variability scales with the feature size and can affect circuit behavior; therefore, metrology tools must capture it. Simultaneously, smaller test structures reduce costs by reducing real estate devoted to metrology.

Complete process behavior understanding also requires tool metrology to verify that the tool supplies recipe-specified parameters and process metrology to measure the wafer's environment. For example, plasma etch system behavior varies from one wafer to the next as the amount and composition of etch residue coating the chamber walls changes. The chemistry and temperature at the wafer surface are the process state's only definitive measures.

Metrology equipment and measurement time are expensive. Fabs are often reluctant to increase a process line's metrology steps. Still, as Brad Van Eck, factory productivity manager at Sematech (Austin, Texas), pointed out, it is impossible to have too much process data. Whenever more data has become available, it has improved yield and process control. A new measurement or new sensor that helps fix a critical process problem justifies its cost many times over.

Once the data are captured, fabs use various tools to identify and classify defects. Wafer maps can be organized by time, toolset, lot position, or whatever scheme seems useful. Stacked wafer maps combine multiple measurements to show emerging patterns. Multivariate statistics packages identify correlations among ostensibly independent process parameters. Automatic defect classification software uses image-recognition algorithms to correlate defects with potential causes.

Yet, these tools only assist, not replace, human experts. Without human guidance, software tools are as likely to obscure as to illuminate the problem. Indiscriminate wafer-map stacking can conceal defect sources that affect only one particular position in a lot or one particular chamber in a cluster tool. Multivariate statistics cannot distinguish between causation and mere correlation. A person must still decide whether the results make physical sense. Often, analytical tools' most important contribution is to free engineers from tedious calculations and provide information they need to think about a problem.

Once defect source information is gathered and correctly interpreted, the fab must eradicate or mitigate the problem. Generally, improvements in baseline yield are obtained by modifying equipment, the process, the design, or all three. Excursions are eliminated by correcting equipment defects and/or improving process control. In both cases, a good understanding of process interactions and dependencies shows which modifications are most likely to work.

At AMD (Sunnyvale, Calif.), identification of key interactions begins early in process development, or even during tool development. At the Sematech 2004 AEC/APC Symposium, Robert Chong, technical staff member at AMD, discussed efforts to identify and model the key parameters in immersion lithography.¹ Water pressure, stage velocity and water flow characteristics can contribute to bubble formation. In collaboration with the stepper supplier, AMD hopes to identify tool sensors and sampling rates needed for effective control of immersion lithography. With that information, sources of variability, potential fault conditions, and incoming substrate dependencies can be monitored.

Once the tool is installed in the manufacturing line, the process control infrastructure's job is to scrutinize it for yield excursions and process variation. Yet, oversensitive monitors affect production time if the tool is shut down for deviations that do not affect yield. As Tom Sonderman, director of automated precision manufacturing at AMD, explained, predictive maintenance is important in maintaining the balance between optimum yield and efficient production. An etch chamber's behavior, for instance, gradually degrades as the process kit nears the end of its useful life. Predictive maintenance algorithms can relate measurable parameters, like etch uniformity and time-to-process kit degradation, and schedule maintenance accordingly, maximizing yield while minimizing lost production time.

A common response to inadequate yield is tool dedication: assigning especially challenging structures to tools known to succeed with them. Although this may maximize a particular lot's yield, it is a poor long-term solution. Each dedicated tool reduces the entire process line's flexibility and potentially diminishes throughput. Ultimately, it is better to determine why a specific tool is successful with a particular structure. A modified process might deliver acceptable results with more tools. Often, Sonderman said, adapting the process to the tool's capabilities is more effective than modifying the tool to achieve a particular process.

The old saying that time is money is especially true for expiring assets, whether fresh flowers, newspapers or ICs. While ICs do not lose their value quite as quickly as yesterday's newspaper, Robert Leachman and Shengwei Ding (University of California, Berkeley) found that DRAM selling prices typically drop 52% in the first year after introduction.² Microprocessors, a segment in which leading suppliers wield price cuts as a competitive weapon, see selling prices fall 67% in their first year. Though foundry capacity prices are more stable — since older technology can be used for less demanding devices — capacity prices still fall 25% in the first year after a new process introduction (Table ).

Falling prices place a premium on fast fab construction, rapid ramp to mature yield, and short cycle time. Leachman and Ding estimate that shaving one day from a product's cycle time increases revenue by ~$5M over its lifetime. A one-day reduction in yield ramp adds ~$1M to the product revenue. For some chips, a few days gained or lost in the ramp phase make the difference between meeting and missing a market window. Gartner Dataquest reports that leading-edge fabs achieve double the revenue per fab and double the ROI of late adopters (Fig. 1 ).

1. Falling behind in fast fab construction, rapid ramp to mature yield, and short cycle time has late adopters lagging increasingly further behind early adopters, in both technology and revenue. (Source: Gartner Dataquest)

Recognizing the value of time, fabs have made substantial investments in metrology and inspection tools and analytical software, significantly improving early yield learning rates. In a study for Sematech, Leachman and Neil Berglund found that fabs implementing the 180 nm node reduced yield loss by 20% in the first three years — more than a year faster than in either the 350 or 250 nm nodes.³ Yet, over the same period, initial yields and mature yields fell. Yield improvement may be faster, but it starts from a lower point and achieves a lower peak. More recent data is unavailable, but anecdotal evidence suggests that the sub-100 nm nodes face more severe yield issues (Fig. 2 ).

2. Random logic yield trends show that fabs operating at the 180 nm node reduced yield loss by 20% over the first three years, taking less time for this than they did at the 350 or 250 nm nodes (different shades within color groups represent different fabs). However, initial and mature yields dropped over the same period. Some expect the sub-100 nm nodes to face serious yield challenges. (Source: Sematech and UC Berkeley)

Lower yields threaten advanced process financial viability. Fab construction and equipment costs continue to rise. Simultaneously, Gartner Dataquest information shows that the revenue generated per square inch of silicon is flat or falling. For acceptable investment returns, fabs must maximize revenue and minimize costs. Increasing yield ramp rate enables the fab to sell more chips during the most profitable segment of the product's life cycle. Simultaneously, increasing yield reduces chip cost, helping to support profits as selling prices fall. Stable, well-controlled processes also extend tool or module life, postponing expensive tool upgrades (Fig. 3 ).

3. Revenue generated per square inch of silicon is flat or falling. Increasing yield ramp rate enables the fab to sell more product during the most profitable segment of its life cycle. (Source: Gartner Dataquest)

Enabling advanced technology

Declining yields are usually blamed on increasing complexity and smaller process windows. Smaller devices are more vulnerable to defect-driven yield loss and parametric variation. An interconnect void or line-edge irregularity insignificant to a larger feature can devastate a smaller one. The number of particles on a wafer is a function of the number of process steps. More steps mean more particles. Copper damascene metallization requires fewer steps for each metal layer than subtractive aluminum metallization. Theoretically, copper metallization should improve yield. Unfortunately, many steps in copper integration are either inherently dirty, like CMP, or new to IC manufacturing, like copper electroplating. These relatively immature processes introduce more, and new, kinds of defects. Meanwhile, the number of interconnect layers continues to increase. CMP was introduced as an enabling technology for circuits with six or more metal layers. Now, complex circuits can require as many as 10 wiring levels.

Although particles and other defects have always threatened yield, parametric yield loss is a relatively new concern. As features shrink, less design margin is available to accommodate timing changes caused by variable interconnect resistance or gate CD. Excess variation reduces the chip's operating speed and value. It can cause the chip to fail when signals reach their destinations at the wrong time.

With increasing process complexity, a smaller budget for process variation must be divided among more process tools. Yet many processes — subwavelength lithography is an extreme example — are being pushed to their limits. Tight feature size and uniformity specifications are achieved only in a small corner of the total parameter space. As the process window shrinks, maintaining the tool within it demands more accurate monitoring of tool parameters and faster response to any deviations.

The first step in identifying and correcting yield-loss sources is differentiating between random and systematic defects. Random defects are exactly that: random. They may originate from airborne particles or photoresist bubbles, but they affect all wafers equally. Random defects fit the normal distribution model assumed by most sampling schemes.

Unfortunately, these defects account for less than half of the fab total. According to Leachman and Berglund, most defects are systematic failures. A handling system consistently scratches the wafer edge, or the first wafer in every lot experiences different plasma processing conditions. Systematic defects — those that have some signature in either time or space — tend to concentrate near the wafer edge. Leachman and Berglund suspect that many "random" defects are systematic defects not yet identified as such.

Random sampling of a systematic defect distribution gives misleading statistics. For example, a defect that affects only edge die will not appear at sample sites elsewhere on the wafer. A random sample tends to underestimate systematic defect problem severity and can fail to capture systematic defect signatures. A sampling strategy focused on systematic defects might take more measurements in particularly vulnerable locations and fewer in areas with more predictable yield. To develop sampling strategies that monitor random defects and identify systematic failures, fabs rely on analytical tools and human experts. Statistics packages can identify patterns more accurately than people, helping to identify systematic defects and field problem recurrences. Human experts use their process knowledge to identify likely defect locations and the most probable sources of observed defects.

According to Leachman and Berglund, generally most serious systematic defect issues are identified and corrected early in process development. As they are eliminated, random defects become a more substantial part of total defect distribution. Still, systematic yield loss remains a major problem, even in mature fabs. Though most yield-improvement plans focus on random defects, inspection and metrology tools already can detect systematic defects — but they must look in the right place. Data collection that recognizes most defects' non-random nature does much to improve process quality.

Normally, processes achieve stable behavior. However, any process can become unstable at transition points, such as the installation of a new process kit. Accurate identification of tool transitions is critical for process control. In a process line with hundreds of tools, several may be approaching transition points at any time. As Sonderman explained, AMD uses models to match the sampling rate to the process's degree of uncertainty. With accurate models, the sampling rate increases during transition periods.

Ideally, the fab dispatching system should recognize and respond to process fluctuations signaling a change in tool state. Armed with that data, software responses might include scheduling maintenance, notifying an engineer, rerouting the product to a more appropriate tool, and/or modifying upstream and downstream process recipes to compensate. Quick and effective response requires a thorough understanding of yield risks and process characteristics.

Building a complete model of everything that happens in the fab is not necessary for substantial performance improvement. At AMD, focusing modeling efforts on just a few key areas gave immediate results. Gate CD and lithography were the most variable and drift-prone, and were addressed first. AMD developed run-to-run control for lithography and etch in parallel with fault detection for deposition processes. Sonderman emphasized that run-to-run control and fault detection systems must be integrated; otherwise, a fault detection system might sound an alarm on an acceptable recipe change from the run-to-run control system.

Next, AMD addressed interconnect defects, particularly in CMP. CMP is a complex process, with many dynamic changes caused by pad wear, topography, etc. Still, Sonderman stressed that all defects have a cause. Once you know what is happening in a tool, he said, you can begin identifying defect causes.

APC's first goal is to maximize a single product's yield in a single fab. Yet, manufacturers often must maintain yield across multiple products, each with unique design-based dependencies. For high-volume products, equivalent performance must be achieved across multiple fabs, sometimes owned by different manufacturers. Moreover, each fab is a dynamic system, with constant changes in toolset and tool performance caused by maintenance, upgrades and planned process improvements. Comparing process results between tools and fabs is difficult. Even a simple film thickness measurement requires the context provided by recipe, equipment configuration, sample location and tool state. A given input parameter might signal a serious fault on one system, yet give completely acceptable results on another.

Samsung's challenge, Seungjun Lee explained at the 2004 AEC/APC Symposium, was to install and qualify new equipment as quickly as possible.⁴ The company constructed input parameter models for each tool, and applied statistical algorithms to historical fault data and metrology data from processed wafers. This allowed engineers to compare new tool measurements to historical benchmarks, streamlining tool qualification.

As fab managers and engineers look at the future of 65 nm and smaller devices, they see no change in trends toward more complex processes demanding more stringent controls. Process control was once nice to have, a way to increase effective capacity and gain a time-to-market advantage; for advanced processes, it is no longer optional, but has become a key contributor to the fab's economic viability.