New Enhancement Platform Starts at the Wafer

With lithographers traveling deeper and deeper into the subwavelength imaging regime, they are being hit with increasingly burdensome challenges, including shrinking process windows, reduced yields and higher mask costs. Optical proximity correction (OPC) and other resolution enhancement techniques (RETs) are being used to achieve the original design intent, but along the way are a huge (and growing) amount of data that must be dealt with, and a debilitating number of mask respins.

Coming into the spotlight at the Photomask Technology conference in October, startup Luminescent Technologies Inc. (Mountain View, Calif.) was touting its Inverse Lithography Technology (ILT) as a breakthrough replacement for RET software. Looking more like a Rorschach test than the jagged mask designs OPC users have become accustomed to, ILT produces designs with rounded edges and disconnected features to create the original design intent on silicon (Figure ).

Standard RET software uses an iterative process to create mask layouts, moving design edges to approximate intended on-wafer results. This method requires multiple iterations, as well as extensive scriptwriting and verification. ILT takes a reverse approach, first evaluating the desired on-wafer pattern, then mathematically determining the mask features needed to produce the intended silicon outcome. It analyzes the entire image rather than just the design edges, generating a globally optimized mask design in a single pass and eliminating the need for extensive scriptwriting.

ILT uses mathematical equations to determine the best mask design to produce the intended outcome in silicon. Shown here are the GDS layouts for the mask on top, with their on-wafer results on the bottom, at two different feature sizes. The wafer images were produced using a standard chrome-on-glass (COG) mask. (Source: Luminescent)

Luminescent has announced a couple joint-development programs — one with foundry Semiconductor Manufacturing International Corp. (SMIC, Shanghai, China), and another with Cypress Semiconductor Corp.'s Silicon Valley Technology Center (SVTC, San Jose). Both programs are focused on solutions for the 65 nm node and below.

Several ILT papers were presented at the conference by Luminescent and research partners, including SMIC, UMC, Xilinx, Cypress, Photronics and Toppan Photomasks . SMIC presented results of the first 65 nm tape-out using ILT, noting that ILT met SMIC's 65 nm process window requirements, providing slightly better CD accuracy and better pattern fidelity through focus. Jonathan Ho of Xilinx presented results of studies done to compare ILT and OPC masks. On a 90 nm FPGA logic layout, ILT showed less corner rounding and less line-end shortening.

A downside noted repeatedly throughout the week's presentations and the questions that followed is the inherently large number of shot counts required to produce such curvy mask features. Optimized for pattern fidelity, the mask write times and database size are extended considerably — a major concern for keeping mask costs under control. But speakers also addressed this issue, noting the flexibility in the ITL tool to adjust the design segment length to optimize accordingly for pattern fidelity vs. write times. With a 30 nm segment length, for example, the write time is about 2× that for OPC, Xilinx's Ho noted. But with 50 nm segments, that time drops to 1.2× that for OPC.

A question raised repeatedly pointed to the fact that ILT really just looks like very aggressive OPC, with an extreme amount of fracturing done to make the design more curvy.

Although presenters generally conceded that yes, aggressive OPC could achieve similar results, there are other factors to be considered. For example, OPC is limited by the script, whereas ILT does not have that limitation, noted Linyong Pang, vice president of product marketing and business development at Luminescent. So in some cases ILT showed similar results to OPC, but in other cases it was better. Also, part of what makes ILT beneficial is its ability to achieve design results in a single pass.

The first product manifestation of Luminescent's technology is the Explorer. It provides complete ILT capability — including full-image inversion lithography, multiple exposure/defocus points, and integrated mask compliance features — but for small blocks. With Explorer, users have printed masks and wafers at 100, 90 and 65 nm, and run simulations at 70 and 45 nm, as well as 110 nm using a 248 nm source. The company is now moving to the beta version of its full-chip product, which should be extendable to the 45 and 32 nm nodes.

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