New 3-D Chip Interconnect Technology

A new approach to 3-D chip stacking and interconnection has been developed by Ziptronix (Research Triangle Park, N.C.), and is capable of enabling over 4 million connections between bonded chips. The company is known for a room-temperature bonding process that results in covalent bonds between dielectrics. The new process, called direct bond interconnect (DBI), expands the technology to make large-scale chip-to-chip bonding possible, including metal-to-metal bonds. "What's different about this process is that the surface is not entirely oxide, but that surface also has exposed metal. After we achieve the bonding across the oxide, we also can get electrical connection when the metal is pulled in contact because of the oxide bonding," explained Paul Enquist, vice president of R&D at Ziptronix.

One of the key aspects of the DBI approach is that it does not require vias to be etched completely through the die, so interconnect routing is not disrupted. Instead of "through-die" vias, this approach relies on "through-silicon" vias, which are adjacent to the transistors and below the transistors, but not above the transistor. In this way, they do not perturb the interconnect structure above the transistors. "When most people do 3-D ICs, they etch vias through the entire die," Enquest noted. "When they do this, that via is then much taller and necessarily much wider. Because it's wider, there are fewer transistors you can make. But more importantly, it also means that you exclude the ability to do interconnect routing. The driving force to do 3-D ICs is to alleviate the interconnect routing problem in conventional 2-D ICs." An additional benefit is that interconnect delays between multiple layers of stacked ICs are minimized.

With this technology, Ziptronix claims the industry's highest density of electrical connections for 3-D ICs bonded in die-to-wafer scale methodology. DBI can achieve 4 million electrical connections per square centimeter, a significant increase in the density achieved with through-die vias used in other 3-D interconnect schemes. A die-to-wafer bond is shown in the Figure .

The bond interface between the die and wafer using direct bond interconnect technology. (Source: Ziptronix)

"The interconnect density achieved by DBI is significantly better than system-in-package technology, which achieves interconnect through wire bonds," said Phil Nyborg, president and CEO of Ziptronix. "As opposed to other 3-D IC technologies, DBI provides chip designers with a sufficient density of vertical interconnections to enable 3-D SoC designs to be fabricated at a significant cost savings, compared to today's 2-D SoC designs."

DBI employs a chemo-mechanical polish to expose metal patterns embedded in the silicon-oxide surface of each chip. When the metal connection points of each chip are placed in contact using the company's room-temperature die-to-wafer bonding technology, the alignment is preserved, as opposed to other bonding techniques that apply heat or pressure that can result in misalignment. The oxide bonds create high bond energy between the surfaces, which brings the metal contact points close to each other to form effective electrical connections between chips after a 350°C anneal.

"It's fundamentally a low-cost process because there are a few number of steps and they're based on a proven manufacturing technique like CMP," Enquist said. "The value proposition of room-temperature bonding is that we can now place the die at room temperature and the pick-and-place machine can continue to bond other die. Whereas if there's a bond process that requires temperature and pressure to achieve the bond, that can substantially reduce throughput and increase the cost."

Ziptronix proved the concept by fabricating what it claims to be the world's first 3-D system-on-a-chip (3-D SoC) as a demonstration for a major networking technology customer for use in the development of wireless communication applications. Ziptronix's innovative 3-D technology provides a viable alternative to traditional SoC and SiP technologies. The 3-D SoC device combines memory, microprocessor and programmable logic die into a single, multilevel silicon die measuring 280 mm², with the second level measuring just 0.03 mm in height.

"The validation of this Ziptronix second-generation device establishes credibility for 3-D SoC and opens the door to the next wave of system integration at the IC level," Nyborg said. "Ziptronix's 3-D integration technology can be used to realize devices with 2 billion plus transistors in the smallest possible footprint."

"This development demonstrates our expertise and focus in 3-D IC technology, and coincides with the initiation of our commercial rollout. Within our licensing business model, Ziptronix is engaging with a select group of initial partners adopting 3-D IC design and manufacturing," Nyborg said.

For more information on emerging technologies, go to www.semiconductor.net/emerging.