Device Modeling and Simulation Meet Shrink, Processing Challenges

Once, device models and EDA software offered limited parameters, such as threshold voltage and mobility. This made it possible to determine (i.e., guess) the impact on factors such as I-V curves. Today, EDA models are "black boxes" that the designer uses without knowing or wanting to know the genie who lurks inside.
 
"EDA companies provide a simulator that implements device models developed by universities or semiconductor companies. We don't develop the models ourselves or research their physics," said Cyril Descleves, product manager for simulation software at Mentor Graphics (Wilsonville, Ore.).

Edmund Cheng, vice president of marketing for the silicon engineering group of Synopsys (Mountain View, Calif.), confirms this. "The physics equations — the model — describing transistor behavior to a circuit simulation program, such as SPICE or HSPICE, are designed to emulate current state-of-the-art device behavior. The models originate from academia or fabs, and tend to be generic. Of course, we must heavily reengineer the models to improve simulation speed and robustness."

Mark Miller, vice president of business development for DFM at Cadence Design Systems (San Jose), recalls 0.25 µm's simplicity. "Complexity increases with each process node. Before, all that was needed were simple look-up table-based device and interconnect models. This changed at 130 nm, with copper; primarily an interconnect-related distortion factor, and not only in the traditional X and Y axes, but also in thickness."

From the perspective of simulating present and future small geometries, EDA companies see the consequences of this on the simulator itself. Increasingly complicated models used to compute things like leakage current, capacitance and other effects use increasingly sophisticated and numerous algorithms. Even so, users expect new simulations to run faster.

"Before, with larger geometries, simulator parameters were limited: width and length, perhaps the source and drain area and perimeter — period," Descleves said. "With smaller geometries, more effects become important and additional parameters extracted from the layout, specific to each transistor, are needed." In advanced models, there can be up to a few dozen different layout-dependent parameters specific to each instance of the transistors. This is much more complex data, requiring additional processing time. Also, some simulators use tables, so they do not compute equations analytically, but tabulate them and produce tables for current and charge variables. For a particular set of input voltages, they interpolate what they computed in this first processing phase of building the tables. "The problem with these instance parameters is that each transistor becomes a specific device," said Ahmed Ramadan, product manager for the device modeling team at Mentor Graphics. "Thus, the size of the tables and the necessary interpolations grow exponentially, causing problems for simulators using these techniques." (Fig. 1 )

1. As geometries shrink, the number of parameters needed to produce accurate models and simulations increase to account for new and varied effects that result from submicron features. (Source: Mentor Graphics)

Computing platforms are meeting EDA software demands. Higher processing speeds, as well as multiple CPUs, have enabled the introduction of resources such as multithreading computation for device evaluation. However, considering the size and pattern complexity of what designers want to simulate, it still makes for a tough row to hoe. EDA suppliers cannot afford to wait for additional CPU power, but must create algorithms that speed up procedures.

Designers inhabit the envelope's edge — if they get software that simulates a million transistors, they try to simulate 2 million. Only elapsed time limits them. If a simulation requires more than one or two days, designers will work to get around it. Occasionally, a simulation will run for weeks for a special design or final device verification, where the interest is not on just one or two clock cycles but in running a full protocol with lengthy patterns to check all combinations and test modes to verify that everything works.

"Sometimes a walkthrough is necessary for a mixed-signal circuit with memory, microcontrollers, some analog parts, voltage differences and drivers, and amplifiers," Descleves said. "These parts have separate flows, and designers try to combine everything together." At a transistor-level simulation, analog cell design and redesign consumes most of the time to ensure specs are met. Several tools can address logic block verification; it can be transistor-level simulations, timing, logic or resistor-transistor logic. Analog cell verification consumes time. "Generally, our users design these cells singly, and then run one or several final simulations either with everything at the transistor level or, usually, using mixed-signal simulation," Descleves said.

Problems arise when designers assemble analog and digital blocks. Checking interfaces is not simple. The only accurate way to do it is with long simulations where the circuit is brought into a state where the interface is active. These circuits cannot be considered as small cells that are put together, simulated and tested individually. When assembled, the circuit must often be fed with a long pattern before verifying that it works. Even memory point design becomes an analog task because, at that level, signals are analog or designers are contemplating analog effects at one bit or word line.

Model developers work at the device level, replicating next-generation pilot devices produced by leading fabs, and do analyses to determine future devices' physical effects and incorporate these into the model. Some issues are related to circuit-level conditions. The developer can assume that, at 65 nm, gate-leakage current will increase, triggering gate-loading effects. There are issues that are dimension-layout-dependent effects, such as well proximity and stress effects. Once everything is included, the models are released to EDA companies.

"In SPICE, there's a thing called the dot model card," said Synopsys' Cheng. "It's a set of parameters or numbers tuned to work with a foundry's processes, used by the model's physical or numerical equations. These can be tuned to a high degree of accuracy, to a particular 'corner' or specific process variation, such as film thickness." When the user, in this case a designer, gets a "model," it is a collection of numbers that work with a particular model and a given simulator — SPICE or HSPICE. Many of these are infrastructures that the designer is not concerned with, but counts on for design accuracy.

"We may be nearing a few forks on the road," Cheng said. "Technologies that use different transistor architectures are being proposed." Unlike actual device engineering, modeling seems the least of the industry's problems — if it can be built, it can be modeled. However, there have been major model changes. One is the stress effect, particularly when unintentionally engineered. "We noticed that device mobility changes depend on how far the diffusion edge is," Cheng said. "Now we also consider things like STI. If this isn't captured by the simulation model and the layout extraction tool, it results in greater process variation. One device will work one way, the next another, and we won't know why." When these changes are correlated with a dimension, it becomes possible to extract those geometric dimensions and provide a better prediction or simulation of device behavior. Transistor variations are correlated to a measurement, making them better understood. Others are still not understood or too complex to model, forcing more statistical approaches to modeling.

"All the extractors, delay modeling, timing and circuit simulation tools scrambled to catch up with manufacturing effects that asserted themselves as non-noise level distortions," said Cadence's Miller. "We confront this same mechanism at 45 nm. You have an assumption about accuracy and error margins, and you must model a collection of distortion factors — some anticipated, others not — for each node. There's a collection of parameters that originated from a mechanical effect — CMP. It caused non-linear distortions of copper interconnects, dishing and erosion effects, scumming and edge placement issues." The distortions were sufficiently predictable to be compensated for within the extractors' algorithms. The core engine that did the resistance and capacitance (RC) extraction inside tools was "smartened up," compensating for those distortions by looking at geographic proximities in the database (Fig. 2 ).

2. Process distortions require increasingly complex models, whose algorithms must be, in turn, executed increasingly faster. (Source: Cadence)

According to David Thon, Cadence's product marketing director of the DFM business unit, part of the trick is determining how to make systematic predictions of these effects. "Computation increases because there's more to include. In previous process nodes, we could ignore the contribution of a wire, or one or two tracks over." This is now impossible, because it creates significant effects. Variables in the equation became so plentiful that many heuristics were tried to avoid additional computation, but it has become necessary.

At 130 nm, wafer flatness and planarization was a fab, not a design, concern. However, at 90 nm and as the move to 65 nm gets underway, another dimension of CMP has become first order: thickness variation. "The effects that resulted in interconnect wires and lack of edge precision is also a Z axis issue," Miller said. "There's perhaps as much as 40% thickness variation across the die and the wafer." Building RC interconnect models with such a sidewall dimension variation would affect crosstalk analysis and everything else.

This one must now be added to the original distortions challenging Z accuracy, and it is more complicated to predict because it is not necessarily systematic across an entire line family — it may be specific to one piece of capital equipment, which leaves a fingerprint of how it scrubs copper off wafer tops. To model what thickness variation effects for that particular line will look like, it is necessary to obtain that fingerprint and determine how to accommodate it at the design creation and implementation phase. This means more complex algorithms and, because the technology is so close to the noise margin, design centering inside the variation range becomes important. So statistical process variation (and remember that only thickness is being considered) must be used to determine how to model everything. The design implementation must be taken and somehow center the entire RC extraction and delay calculation and timing results — mostly interconnect — within the range of likely variations to maximize yield.

If multiple interacting distortion engines are overlaid, since 193 nm light is used for printing, everything from 180 nm down requires significant optical proximity correction (OPC); lithography becomes another distortion source. At λ/2 at the 90 nm node, λ/3 as you pass 65 nm, the number of layers, with respect to high-effort OPC, rises dramatically. At 45 nm, one is pretty much looking at all layers and will need some level of model-based treatment or r-based combined model.

"Regardless of corrections, the result won't be nice straight edges and square corners," Miller said. There are now rounding effects and necking, pullback of edges and lines in places where the designer has no idea it happened. "Everything's now instance-specific and adjacency-dependent, and it'll be difficult to deal with it in a post-processing sense alone," he added. Thus, one must take the interaction of those distortion factors and pull them back into the design implementation phases as rapidly as possible to model lithography-based distortion factors along with CMP-related ones, and center the design within the space of statistical variation probabilities.

"The extraction and physical verification tools traditionally have projected manufacturing effects into the design space," Thon said. "Extraction enables an electrical impact evaluation. Physical verification, especially DRC rules, projects back into the line and space the intended effects that you want in manufacturing." Computationally, both are becoming difficult, not just because more effects are present, but because more rules are involved. The complexity of just maintaining accuracy as the process line varies and shifts through its lifespan is staggering. At 0.25 µm, there were a few hundred rules. Now there are anywhere from 2000 to 8000, and new physical verification technologies are needed.

Jamie Metcalfe, vice president of marketing, Allegro IC package codesign, at Cadence, views the relationship between packaging and the silicon's process node: "Look at what's involved in going to 65 nm, 45 nm and beyond. The number of I/Os in the silicon will continue increasing. Today, even with 90 nm silicon, we have devices with 1000+ I/Os." This means further adoption of flip-chip technology, but at 45 nm, we face the problem of how to connect that kind of finer-pitch bump array directly to the package.

A different approach is necessary, requiring more accurate characterization of package interconnects — a need to analyze and verify noise margins and skew. If voltages are lowered, the chip becomes more sensitive to power stability, because margins have been reduced. At 2.0, 1.8 or 1 V and below, not much drift can be allowed during switching; otherwise, bit errors result. Designers will have to put some real cycles into delivering power from the PCB through the package down to the die. Some are doing detailed analysis of dynamic IR drop at the IC's core — when it switches — but will not take the package into account. Nowadays, the package is truly an active element, not just a mechanical connector to the PCB.

Packaging must be modeled to determine how it affects power delivery to the die's core areas, especially those areas with the highest power consumption, such as CPU modules. More accurate modeling tools are necessary. Three years ago, it was acceptable to model a package using 2-D field solvers. Modern packages have intricate via structures and complex geometries requiring a 3-D extraction engine; also, one is now in the higher frequencies realm. "We have customers doing designs requiring serial interfaces on the I/Os of the chip, pushing the data out of the chip at 12 Gb/sec," Metcalfe said. "At that frequency range, you move from time domain into additional frequency domain simulation. It's an analog problem."

Development of fast full-wave extraction tools is needed to extract large design areas, such as a full-wave S-parameter model, and plug that into the signal integrity simulation of the interconnect from buffer to buffer. Timing as well as noise must be considered; with designs requiring BER prediction, everything must be considered. Today, when doing a 130 nm baseline process node, designers often estimate packaging interconnect. However, at 90 or 65 nm, that interconnect must be exactly modeled to avoid wasting valuable design margin.

Then there is the final power delivery to the IC core, and there it will be necessary to simulate the dynamic IR drop using a true package model. Not a lumped model estimation, but extracting from the package a true power and ground network representation that can be plugged into the dynamic IR drop engine to simulate the voltage drop effect of the ideal voltage source going through the package onto the IC core.

As we continue toward deep submicron, models will become increasingly complex, requiring additional time for processing and evaluation. There will be more interaction between device models and layout extraction tools. This will cause problems in algorithm development and simulation speed. Model developers now face the problem of introducing multiple deep submicron physical effects into device models, while keeping model execution speeds at a reasonable level.