Computer Simulation Accelerates Equipment and Process Design

Until recently, the semiconductor industry relied heavily on empirical methods for the design of manufacturing equipment and processes. This empirical approach was needed because of the rapid pace of innovation and our relatively poor understanding of the fundamental physical and chemical phenomena underlying the manufacturing processes in most circumstances. Increasing competition augmented by technological challenges to meet stricter requirements for multilevel interconnects with smaller device size and new materials on larger wafers have made the conventional trial-and-error method prohibitively expensive and time-consuming in the semiconductor industry.

Serious attempts in equipment and process modeling and simulation (M&S) are therefore being made to overcome these technological and economic barriers. This approach is similar to what's used in several other industries (e.g., aerospace, automobile and pharmaceutical) that had to overcome significant technological barriers in the past without increasing cost. Computational modeling provides a better understanding of the manufacturing processes, supplements the conventional experimental techniques in expediting the design and development process, and significantly reduces overall development time and cost.

Semiconductor wafer processing includes a transistor cycle in the front-end-of-line (FEOL) and multiple interconnect cycles in the back-end-of-line (BEOL). The FEOL unit processes include gate oxide deposition, ion implantation, rapid thermal processing, epitaxial growth, high-k deposition, chemical mechanical polishing (CMP), self-aligned contact, high-aspect-ratio trench, and silicon etch. The BEOL unit processes include plasma etching of conventional (SiO₂, TEOS) and low-k dielectrics, physical vapor deposition (PVD) of barrier (e.g., tantalum) and seed (e.g., copper) thin films, electrochemical deposition (ECD) of copper wires, CMP, plasma-enhanced and thermal chemical vapor deposition (CVD) of dielectrics, thermal CVD of metals (e.g., tungsten), atomic layer deposition (ALD) and plasma clean processes.

Most unit processes are conducted in complex physical environments. M&S of these processes therefore needs to adequately account for gas flow/mixture, heat transfer, chemical reactions, electromagnetism, plasma physics and chemistry, gas phase and surface interactions, structural strength, vibration, tribology and their interactions. The advancement of computational fluid dynamics (CFD), direct simulation Monte Carlo (DSMC), finite element analysis (FEA), plasma modeling, chemistry and feature scale simulation codes have helped the M&S effort tremendously in the semiconductor industry. With increased sophistication of simulation codes, some of the interdisciplinary phenomena are well addressed for many unit processes. In recent years, substantial progress has also been made in coupling unit process models so that integration-related issues can be addressed. Since the equipment design directly affects the process on the wafer, equipment and process modeling have begun to complement each other.

Processing equipment used for unit processes are primarily simulated using two-dimensional and three-dimensional CFD/FEA codes (e.g., CFD-ACE,¹ Fluent² and ANSYS³) available from several commercial sources. These CFD/FEA codes are numerically sophisticated, and the underlying physical models (e.g., fluid dynamics and heat transfer) are detailed. These codes are used to address the intricate details of processing equipment, such as those used for CMP, PVD, CVD, ECD, ALD and etch. Numerical particle methods like DSMC are also available in advanced 2-D and 3-D versions for reactor scale modeling applications. These codes usually have less sophisticated meshing capabilities compared with the CFD codes, and are typically available from academia and government laboratories. Their applications are for the low-pressure semiconductor equipment processing (i.e., <5 mTorr) that are seen in etch, PVD and high-density plasma CVD.^4,5

Because of the nonlinear nature of the problems and their numerical complexity, plasma-related processes were initially simulated using university-based codes.^6,7 In-house computational tools,⁸ commercial software¹ and user modifications to commercial software⁹ are now the norm. An initially non-commercial user base dictated that such plasma modeling codes have less sophisticated meshing capability and user interfaces than commercial software provides. Adequate models now exist for most inductively and capacitively coupled industrial plasma etchers and variants of PVD tools. Computational modeling has also been used to understand the environments plasma deposition reactors and plasma cleaning, as well as assist in equipment design.

Among the many techniques that have been used for simulating feature-scale problems, string, level set and Monte Carlo based methods are the most common. Several sophisticated 2-D and 3-D simulators have been developed in academia and industry (e.g., CFD-TOPO,¹ Papaya¹⁰ and Evolve¹¹), and these codes can address not only individual unit processes but also sequences of unit processes to allow integration-related studies. For example, 2-D and 3-D feature-scale models for plasma etch processes can simulate the formation of dual inlaid and other complex structures.

Despite the tremendous progress made in the area of equipment and process modeling, many challenges remain in more widespread applicability and use of this technology. Although flow, thermal, structural, electromagnetic and vibration models can predict the physical phenomena with a high degree of accuracy, chemical and plasma models can generally only provide the trends. The primary challenge in process modeling is the lack of quantitative physical understanding and data about the many fundamental physical and chemical processes that are pertinent to the unit processes. By their very nature, industrially relevant unit processes are chemically complex, often nonlinear, and involve many intercoupled physical phenomena. The current methodology of empirically developing gas phase and surface chemical mechanisms using experimental data has limitations, especially outside the regime where the models have been validated. Inadequacy of experimental diagnostics programs to support the model development effort and the large number of technologically relevant processes and materials contribute to relative immaturity of many process models. Fundamental ab initio modeling is an attractive option for developing physical and chemical mechanisms and providing understandings of how the mechanisms work,¹² but the full potential still needs to be developed.

One additional challenge for M&S revolves around how to organize such activities in industrial environments. The authors here all participate in centralized, corporate modeling organizations. The alternative approach is for each business unit to provide its own modeling resources, which allows specialization in the particulars of the unit's business needs. However, if the modeling practitioners are not engaged full-time in modeling, the complexities of today's models make it difficult to exploit their full potential and for modelers to keep up to date with new developments. We expect that the centralized approach should remain the more efficient organizational structure for years to come.

Here we will show a variety of M&S studies for FEOL and BEOL applications to demonstrate how simulation accelerates design and development of semiconductor equipments and processes. Years of work have been devoted to the development of these models. By virtue of the problem and process complexity, the models are usually supported by significant levels of in-house calibration to be quantitative.

In recent years, the semiconductor industry has made considerable progress toward developing high-k dielectrics (e.g., HfO₂) that can replace SiO₂ as the gate dielectric. One technique that has helped increase the gate dielectric's k level for current-generation products and make the dielectric more impervious to boron penetration during ion implantation is nitridation of SiO₂. Plasmas, whether inductively coupled, capacitively coupled or remote, remain the most promising means of nitriding the gate dielectric. Recently, an integrated plasma equipment/surface physics model was developed for nitridation of SiO₂ in a decoupled pulsed plasma source.¹³ The dielectric nitridation mechanism was developed using several experimental diagnostics, including X-ray photo-electron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS). The pulsed-power plasma processing tool was simulated using Io,⁸ a 2-D plasma model that has been developed at Freescale Semiconductor (Fig. 1a ). The plasma equipment model was coupled to a 1-D surface physics model, which considers reaction of neutral and charged nitrogen species with SiO₂ and nitrogen diffusion within the film. The model has been thoroughly validated using experimental measurements (Fig. 1b ) and it adequately captures and explains the trends of nitrogen profile with plasma power, gas pressure, nitridation time and dielectric film thickness. The model shows that atomic nitrogen adsorbs near the dielectric surface and N₂+ ions are responsible for the tail in the nitrogen concentration profile. Insights gained from computational modeling have played a prominent role in the design of plasma nitridation processes for the latest CMOS technologies at Freescale Semiconductor.

1. A 2-D plasma model (a) shows the N2+ ion density in a pulsed inductively coupled plasma during the power-on phase (10% into cycle) and after the power has been turned off (40% into cycle). The impact of peak RF power on the computed and measured nitrogen concentration profile in an SiO2 gate dielectric is shown (b). The pulse duty cycle is 20%.

Dielectric etching and metallization for dual inlaid processes

The impact of trench etch chemistry on trench-via interface integrity in a dual inlaid process integration is shown in Figure 2a. A less polymerizing process results in the erosion of the trench-via interface, while the more polymerizing chemistry results in the protection of the interface but allows for fence creation. SEMs for a process comparable to Figure 2a are included in Figure 2b . Differences exist between the model and simulation results and are unavoidable because of the fast pace of development in a modern-day fab. However, the simulations can successfully narrow the parameter range considered by process engineers by exercising virtual splits that are time- and cost-prohibitive experimentally.

2. Simulation (a) and experimental results (b) for the dual inlaid etch process after trench etch. In the simulations, red represents the distance “into the page,” and green represents the plane of the page.

An example of a process in which simulation uncovered how to take advantage of the operation of a metallization tool to optimize step coverage is presented in Figure 3 .¹⁴

3. Comparison of simulation (a) and experiments (b) for the low- and high-target-power PVD process comparisons. The simulations represent the thickness of the barrier material on the topography resulting from the dual inlaid etch process.

In BEOL metallization, all etch steps in the dual inlaid etch process sequence impact barrier and seed step coverage, which in turn impact reliability and via resistance. Equipment simulations show that, at a relatively low target power, a regime exists in which effective resputtering occurs. This is critical for minimizing via resistance and maintaining barrier integrity. That a lower via bottom barrier thickness is deposited at low target power is shown in Figure 3a. It is accompanied by a higher sidewall thickness indicating a high degree of resputtering, as indicated in the SEMs shown in Figure 3b . The ultimate arbiter of success for simulation-guided process development is electrical measurement of fabricated devices. Electrical measurements of the via chain resistance showed significant via resistance decreases for the simulation-borne process. The primary business impact of process integration simulations described above ranges from process innovation to a reduced number of required development lots and thereby reduced cycle time.

Copper ECD is currently used in the damascene process sequence to form on-chip interconnects. Transient and steady-state models in 2-D and 3-D of the secondary current distribution with ohmic potential drop in the electrolyte and the seed layer were used in modeling the 300 mm Sabre xT system from Novellus Systems. The models examined effects of metal layer non-uniformity, electrode contact geometry, and overall scale-up from the 200 mm Sabre tool. These models were performed with CFD-ACE¹ and an in-house developed user subroutine enhancement to that commercial code. The secondary current models used experimentally measured Tafel curves to describe the overall electrochemical behavior of the plating cell. This method was chosen to significantly reduce the model's complexity and run time compared to simulations with current flow, fluid flow, mass transfer and additive chemistry, without losing the essential chamber design elements. Transient simulation results in Figure 4 showed that the models match well with experimental data for the 200 mm chamber for the transient buildup of the plated metal layer. For a given cell configuration, the scale-up of the deposition non-uniformity was <2× in a 300 mm system, despite the 1.5× increase in geometrical size, and a 2.25× increase in total plated current. The reason for this is that more of the current flow is short-circuited to the outer radius of the metal layer in 300 mm, causing a lower voltage drop in the center of the layer, and a reduction of the simple 2.25× voltage scale-up compared to a 200 mm case.¹⁵

4. Comparison of 200 and 300 mm transient plating models.

Steady-state models in 3-D were used to examine the effect of electrode contact geometry on deposition uniformity at the onset of plating. With sufficiently large numbers and a semi-continuous distribution of electrical contacts to the seed layer, azimuthal asymmetry effects on uniformity were eliminated.¹⁶ Such simulation results provided better understanding of the copper ECD process, and helped reduce the design time and overall time to market for the 300 mm Sabre xT system.

Typically, in tungsten multi-station sequential batch systems, some deposition stations sit idle while a newly loaded wafer is heated up and exposed to a protective silane flow. This idling is necessary to prevent the device attack and gas phase nucleation that can result from early introduction of WF₆ to the chamber. In the 300 mm chamber design for Novellus' Altus tool (Fig. 5 ), this problem is addressed by altering the chamber geometry to greatly improve the isolation of individual deposition stations. This allows incompatible processes to take place simultaneously on adjacent stations with minimal crosstalk, providing a substantial improvement to the throughput of the system.

5. Geometry of the 300 mm chamber, with the upper portion of the chamber raised for clarity. The volume has been reduced to minimize station-to-station crosstalk and residence time.

Models for the chamber were performed in Fluent, including flow, heat transfer, mass transfer and thermal CVD.¹⁷ A kinetic rate expression for this tungsten thermal CVD process was developed and validated using experimental step coverage measurements.¹⁸ This rate expression was supplied to the Fluent software through the use of a user-defined subroutine. Figure 6 shows WF₆ concentration across the top plate purge region and the showerheads. It also shows the pedestal with flow pathlines colored by silane concentration on the stations with the silane protective flow and a highly uniform tungsten metal deposition rate below the showerheads flowing WF₆. The development of a strong level of understanding for the tungsten thermal CVD process through the coupling of theory, experiments and subsequent 3-D modeling shows the power of such processes to improve tool operation in general, and tool throughput in this example.

6. Modeling results for the 300 mm chamber, with the upper portion raised for clarity. WF6 concentration is shown in the plane of the top purge plate. Tungsten metal deposition rate and silane flow pathlines are seen near the pedestal.

Summary and conclusion

Tremendous strides have been made in the semiconductor industry to make M&S an integral part of the equipment and process design methodology. M&S has been able to address a wide variety of microelectronics manufacturing technologies, including plasma etching, thermal and plasma-enhanced CVD, ECD, PVD and plasma materials modification. The models have become increasingly sophisticated over the years and are now capable of addressing multiple physical processes simultaneously. These models can also address integration-related issues that involve multiple processes, realistic 3-D geometries, and large spatial and temporal scales.

Most companies involved in M&S have experienced that this work leads to enhanced product understanding, provides a cost-effective method for hardware and process optimization, is an effective conduit to innovation and product differentiation, and results in cost and time savings. It is expected that, as ab initio chemistry models mature in the coming years, the semiconductor industry would be able to utilize fundamental-level atomistic understanding of key manufacturing technologies for product development and optimization. The success of M&S in the semiconductor industry is a product of concerted effort by the industry and academia to understand the key fundamental phenomena of relevance to semiconductor processing. We hope that this investment in fundamental understanding will continue in the future, nourishing further growth of M&S and its application to design and development of equipments and processes.