NiSi FUSI Sets Performance Records

Dramatic improvements in transistor performance through the use of fully silicided (FUSI) metal gates will be presented at the International Electron Devices Meeting (IEDM), to be held Dec. 5-7 in Washington, D.C. Intel's use of nickel silicide (NiSi) FUSI (Figure) set a new record for drive current. Texas Instruments has also implemented NiSi FUSI gates using a novel integration process. Other work on FUSI gates is slated to be reported by IBM, Toshiba, Philips, IMEC and other companies.

The record-setting Intel work is, according to the authors, the first comprehensive evaluation of silicon CMOS devices integrating a NiSi metal gate (FUSI) process with highly strained silicon channels. The strain was process-induced uniaxial strain, and the transistors had ultrathin 1.2 nm gate oxides. Together, the strain and metal gate enabled record-high drive currents: in NMOS, I_dsat=1.75 mA/µm, and in PMOS, I_dsat=1.06 mA/µm (V_DD=1.2 V, I_off=100 nA/µm). The authors say these devices also have the best I_dsat vs. I_off characteristics reported to date in the industry.

To fabricate the transistors, a 1.2 nm thick SiON gate oxide is used with 35 nm physical gate length transistors. The PMOS transistors incorporate epitaxially grown source/drain (S/D) regions to induce uniaxial compressive strain in the channel region while the NMOS transistors use a capping layer to induce tensile strain in the channel.

XTEM through gate stack of NiSi gate PMOSFET with strained epi SiGe source/drain regions. As evident, PMOS gate is fully silicided. (Source: Intel)

There are two reported process options to implement nickel FUSI. The researchers said both result in equivalent transistor performance. In one option, nickel can be deposited on the wafers after polysilicon and S/D junction activation. By carefully optimizing the polysilicon and nickel film thickness and the silicide thermal budget, full silicidation of the polysilicon gates is accomplished while preventing the formation of excess NiSi in the junctions. Alternatively, the S/D silicide and gate silicide formation steps can be decoupled by using a damascene process to selectively expose the surface of the polysilicon gates after the S/D junctions have already been silicided. The latter approach enables independent control of nickel thickness for S/D and polysilicide.

In the FUSI approach, to be reported by Texas Instruments, a cobalt silicide was integrated as a nickel barrier. The transistors demonstrated 15% (NMOS) and 31% (PMOS) performance improvements over polysilicon with a 35 nm gate length. The TI authors note that the challenges of integrating FUSI into the CMOS technology include FUSI integration with minimal impact to the conventional CMOS process, robust FUSI unit process free of poly linewidth and n/p doping dependence, and thorough evaluation of intrinsic NiSi FUSI material property and impact on CMOS devices. TI fabricated NiSi FUSI transistors with a modified manufacturing CMOS process using nitrided gate oxide (SiON) of 1.7 nm equivalent oxide thickness (EOT). NMOS polygate was predoped by arsenic and phosphorus. A cap layer was then deposited prior to gate patterning. The conventional CMOS process follows through silicide. CoSi₂ was then formed on the active substrate, while the cap layer protected the polygate. A selective wet clean process removed the cap but left the CoSi₂ intact.

After a nickel thickness of >60% of that of the poly was deposited, an optimized two-step process was performed to fully silicide the gate. CoSi₂ in the active region was shown to be effective in blocking nickel penetration and preventing further silicidation of the silicon substrate. After FUSI, conventional processing continued through the back end.

In other work by IMEC, the Silicon Nano Device Lab at the University of Singapore, Philips, and the University of Texas at Austin , researchers plan to report on how the addition of ytterbium to nickel FUSI allows for tuning the work function (WF) from midgap (NiSi ~4.72 eV) to n-type band edge (~4.22 eV) on thin SiON, maintaining the same EOT. The researchers did not observe any interface adhesion issues found in other reports when WF was modulated by dopants such as arsenic or antimony. They say that the reliability is similar to nickel FUSI. This is a promising technique for nFET gate electrode formation, and enables dual-gate CMOS technologies for 45 nm and beyond in a manufacturable way.

Editor's note: The material in this report was provided by conference organizers in the form of abstracts.