Raúl Camposano, Senior Vice President and CTO, Synopsys

Raúl Camposano (Source: Synopsys)

Raúl Camposano joined Synopsys in 1994, and led the design tools business unit — Synopsys' entire suite of design tools — from 1997 to 2000. He is currently the CTO, senior vice president and general manager for its silicon engineering group. Before this, Camposano was a director for the German National Research Center for Computer Science, professor of computer science at the University of Paderborn, and a research staff member at the IBM T.J. Watson Research Center. He holds a BSEE and MSEE from the University of Chile, and a Ph.D. in computer science from the University of Karlsruhe, Germany. Camposano has published more than 70 technical papers and written or edited three books on EDA, and is also an advisory professor at Fudan University and the Chinese Academy of Sciences . He was elected a Fellow of the IEEE in 1999. Synopsys Inc. (Mountain View, Calif.) specializes in semiconductor design software and professional services used in the design of systems on chip (SoCs) and electronic systems.

SI: We understand that you advocate a tighter link between EDA and manufacturing.

Camposano: Yes. These were always separate, just as place-and-route and logic synthesis used to be two different things. As timing and signal integrity problems came along, we had to tighten them to calculate exact delays, exact power, and cross-talk between signals for signal integrity. This can only be done by accounting for physical properties while doing logic design.

Regarding manufacturing, manufacturability was a problem solved mostly in the fab, much like place-and-route "solved" timing and signal integrity issues. Design dealt with manufacturability essentially by respecting design rules. Now, manufacturability issues have crept in, and it's no longer possible to let the fab take care of them. For good yield, you must do things during the design phase.

SI: Such as?

Camposano: Systematic yield is becoming increasingly important. We also know that preferred design rules can dramatically increase yield, but that if they're applied throughout a design, the situation becomes too rigorous. We know that spacing lines and putting in double vias are important for yield, but they must be applied judiciously or the design becomes unacceptably large. Something more complicated is design-driven OPC, where you look at how critical a feature is in the design, and apply OPC depending on criticality instead of a recipe that's solely based on feature printability and certain tolerances. You vary some tolerances to suit requirements.

SI: MOS devices' simplicity and the capability to automate complex procedures has enabled smaller shrinks and integration levels. Now, design software is challenged by the sophistication required, where transistor parameters shift as a function of time, and performance must be included at the transistor level and interconnect level, and power dissipation as well as speed performance must be considered, alongside other various trade-offs. How do you view this situation from the EDA perspective?

Camposano: Today, most of this is taken into account through margining. For instance, when you model your transistor for SPICE, you provide margins to account for these factors — transistor's aging, reliability, exact power and speed. Now, as we scale down, the margins, when compared to the actual parameter, are becoming too large. Several things can be done. Regarding reliability and aging, software today computes current densities, which gives a good idea about how quickly or slowly things will age. If a greater level of detail is needed, TCAD software can be used to do device simulation and simulate the aging, relieving you from doing as many experiments as would have otherwise been necessary — you can simulate it.

Another example is the extraction of device parameters using TCAD by considering the actual shapes that are printed. Normally, when RC extraction is performed, one assumes idealized features such as rectangles. At best, one may take into account certain effects that turn a rectangular cross-section into a trapezoid, but these are all pretty simplified geometric features. Today, at least for one or a few devices, one can do lithography simulations, determine which features really print, which will be a complex curve for a gate. Then the parameter extraction can be done through device simulation with TCAD providing the exact shape being printed, not an idealized rectangular gate. We've experimented with this, and you get between 5-10% differences, which are recoverable margins because this more accurate model is available. All these effects can be taken into account by EDA software, making it more accurate with fewer approximations, recovering the margin, and modeling effects such as reliability, current densities, etc., more accurately.

SI: EDA complexity has risen exponentially, allowing device makers to continue the work in progress. Doing a 2-D design is difficult, and 3-D is over an order of magnitude more complicated — EDA currently lacks the visualization, automation, and capture capabilities. Is relief on its way?

Camposano: Right now we're doing what I call, "21/2-D." You can stack a memory chip on top of a logic chip and connect them. Modern system-in-a-package allows you to do this — stack chips one on top of another instead of putting them on a PCB, like in the old days. If you reach for "true" 3-D, where you just keep on layering, there indeed are physical problems because we mostly rely upon CMP to stack, say, 10 layers of metal, and I am unsure what the limitations are in principle. Some companies are producing memory structures by using polysilicon and not just metal layers on top of each other. Then you can have relatively slow switching of the active devices, not just metal, in 3-D layers. However, that's limited to things like ROMs and simple memory structures. Most likely we'll stack chips, much in the way we're beginning to do with memory, to get these "21/2-D" structures.

If we consider detailed transistor and device simulations, the traditional simulators would essentially use 2-D simulation in terms of accuracy, where you just have a cut and simulate one particular cut line of a device in 2-D. This is because that's all available computing power could do in the past. Currently, TCAD models are 3-D. You can do 3-D grids and simulate a device in 3-D to determine all the spatial effects of what goes on inside; this provides additional accuracy. From there it is possible to simulate more complex structures in 3-D; these capabilities should be useful for future devices other than just the ordinary planar MOSFET, for things like finFETs or multigate devices.

SI: We're moving toward the nanometer regime. How is Synopsys preparing for this transition?

Camposano: We're seeing the bulk of the industry migrating toward 90 nm, and already there's some design activity at 65 nm. We've seen a few experimental tapeouts in 45 nm. EDA software needs additional accuracy as we move to smaller technology nodes. Increasingly, manufacturability effects also become relevant at higher design levels. If you look at OPC, RET, etc., these effects are also increasing. We'll probably stay with current lithography technology down to 45 nm, probably with immersion in addition. But with 193 nm lithography, you must do additional OPC, more RET, and we're providing this in our OPC platform. All this involves additional computation, making distributed computing more important. The capability to execute software on different computers in parallel becomes key to providing reasonable computing times for increasingly complex problems.

SI: Are you adding further distributed computing capabilities to your software?

Camposano: Yes. Much of it, particularly OPC and DRC software, has distributed computing capabilities, so it can run on many computers — hundreds or even thousands in the future — to reduce computing time to a few hours for complex problems. In addition, place-and-route will incorporate an ever-increasing number of rules and models to augment its DFM capabilities, for example, to enable, during place-and-route, manufacturability checking based on lithography models to determine if features will print properly.

SI: Algorithms are becoming more complex and difficult to produce. Are we headed toward a brick wall?

Camposano: Look at what's taking place in the computer industry. It gives a good indication of where that paradigm is headed. In the past, the computer industry provided you with increasingly faster single CPUs; they accelerated the clock and provided larger memories — from 32 to 64 bit — addressing bigger caches. You had superscalar that allowed you to do two or three operations in parallel, but essentially it was just one faster computer. Now it's difficult to raise clock speeds from where we are. So multicore computers are making their appearance; today it is two CPUs and tomorrow four, eight, 16 cores in one chip, and you'll put several chips in a box. The standard low-cost computer today is already two computers in one box; by year's end it'll be four.

For EDA algorithms, this means that we must provide software that runs efficiently not only on one CPU, but can be distributed to several and is either multithreaded or distributed or uses some other paradigm to enable it to run in parallel and accelerate the processing. In our case, design rule check and OPC can be distributed very efficiently across several hundred CPUs if need be.

SI: Any trade-offs?

Camposano: The software may not execute as fast on one computer, but run very fast on 10 or 100 computers. In the future, more and more software will run on multiple computers, as distributed computing will continue getting cheaper. All chips produced in some future will be multicore and/or multithreaded, making it easier to run several threads/copies on one chip.

SI: Design and test requirement for architectures 90 nm and below are becoming more demanding. How are you meeting the challenge of signal integrity concerns that arise at these geometries?

Camposano: To exactly deal with signal integrity would require something like an extensive SPICE simulation, which would precisely show all the electrical effects between wires, capacitances, and so forth. This is too costly to do on a complete chip, or even for a few tens of thousands of transistors. The alternative is static-timing analysis, which approximates signal integrity effects through windowing techniques but does it statically, not with a simulation, calculating worst-case effects, critical paths, and other similar parameters. This handles effects of how signals are delayed comparatively to each other and also signal integrity effects across wires — caused by cross-coupling capacitances — whether delayed, accelerated or just falsified. In the future, statistical techniques will gain in importance and instead of just corner case analysis for process values, maximum and minimum voltages, and temperatures, we will look more at the actual distribution of those parameters and do statistical analysis as well.

SI: How are you meeting the changing requirements in the areas of digital design, SoC functional verification, custom analog design, and DFM?

Camposano: Functional verification in digital design is an important area. It points us to system-level design or ESL. Here, we're transitioning toward higher abstraction levels. We're developing tools that support System Verilog and have tools that support simulation in SystemC. There's considerable work being done on semi-formal or formal verification on things like equivalence checking between models and property checking. All this is primarily focused on functionality for digital. Once you add the analog part, analog/mixed-signal simulation becomes essential.

Much of analog simulation is done in SPICE. Verilog-A is coming on strongly; it's a standard and simulator-independent — its models will run on any simulator — while SPICE is simulator-specific. So co-simulation between SPICE and Verilog-A and Verilog for the digital area is important for analog/mixed-signal verification. As we move forward, Verilog-AMS and VHDL-AMS provide an analog/mixed-signal simulation that is language-based, which enables a description of the whole design — analog and digital — in a mixed fashion, and then simulates it. The simulator distributes the digital and the analog part to the different engines. On a higher abstraction level, such as system Verilog, system C, C++, some combine analog and digital simulations to simulate complete systems.

Regarding DFM, it is necessary to account for manufacturability effects in the lithography tools such as OPC, but also in physical design — in place-and-route and even logic synthesis.

SI: What are your DFT and BIST strategies?

Camposano: The roadmap predicted at some point that by 2010 testing a transistor would be more expensive than building it. To cope with the increasing cost of test, historically, we've moved from functional test, where an external tester would provide the stimuli sequences to a chip and would test the responses to decide whether it passed or not. Scan-based test significantly simplified test by allowing it to scan in and out all the state signals in the chip by linking it in a scan chain. This is today's state-of-the-art for logic. For memories, BIST is state-of-the-art.

The trend is toward some kind of BIST, so that you can do more of the testing within the chip. The first simple version of that, for logic, is test compression. Thus, you need not scan in the complete sequence, with part of the sequence generated on the chip itself and the analysis of the results also done partially on chip. The next step is full-blown BIST not just for memory, but also for logic. Since most chips already have embedded processors and software, this can be supported by the embedded OS, as well as by the EDA tools that do the DFT.

SI: Packaging has become an integral part of the circuit. Where do you see packaging going over the next three years or so?

Camposano: We look at packaging as what lies between the board and the chip. In the past, we've mainly concentrated on chip design. Different software does PCB design. The package matches the two, and it is increasing in importance because on the one hand, the number of pins that are being integrated on a chip is increasing and, on the other hand, the speed of the chip needs to be matched with that of the board. There are packaging tools that simulate the I/O circuitry with the package's actual electrical properties. Tools that can simulate several chips stacked in one package are becoming more necessary.

SI: Which do you consider the biggest problem in your area?

Camposano: Developing a generic way to distribute programs. Being able to take any algorithm or EDA application and run it on many different parallel computers, scaling to the thousands if necessary. If we could scale any application, it could be speedily executed in a cost-effective fashion, solving a large part of the design cost equation. If I have a place-and-route run that takes three days and I could run it in 100 computers, I might get it down to an hour. This would have an incredible effect on costs.

SI: You teach in China. Will EDA also move to Asia?

Camposano: There's some EDA development activity there. Universities are teaching how it is done, and coming up to speed quickly. I give a couple of lectures there every year in Fudan. We have organized trips for professors to go there and lecture, and Chinese students come to study in the U.S. Overall, the state of the knowledge there isn't too far behind ours. China will catch up very quickly. Will EDA go there anytime soon in a significant way? That is yet unclear, because EDA has a number of complexities — remember it is software, not manufacturing. However, there are already a few small EDA companies in China that are beginning to function. We will have to face that competition in the same way we have had to face all others.