Metrology Tools' Viability at 32 nm and Beyond (Part II)

Intel conducted a series of studies to determine the viability of metrology technologies at the 32 nm node.¹ Last month, I presented results for CD-SEM, scatterometry and AFM . I will now focus on their results with dual-beam and high-voltage CD-SEM (HVSEM) technologies.

Dual beam is attractive, because it enables cross-sectioning-like activity on a wafer. It can now do the in situ sample processing, including activities such as decorating the sample, coating it with a conductive layer, and doing automatic pattern alignment and automatic CD measurements all in one stop. This combination is efficient from a time-saving perspective, because a skilled technician would need many hours to go through all the sample preparations to get a cleaved, coated, decorated and well-characterized measurement with CD values. From the perspective of CD metrology, the obvious use for this tool is in a lab or failure analysis setting. The question is how to use a destructive technique for CD measurements in a fab setting. There is no general applicability for it; an active device would be damaged by it.

However, if this kind of feedback is necessary and one must see what a device looks like under its surface, dual beam provides a fast way to perform this if one is willing to sacrifice a few die for information. Nevertheless, in an R&D setting, it can be a time saver, making it logical to place in the fab to get instant and very detailed feedback that otherwise would have taken a day.

AFM’s capability is primarily dependent on tip technology and the control mode. To measure non-reentrant profiles, it is possible to use straight, sharp tips like carbon nanotubes. (Source: Hitachi)

HVSEM has been bandied about for some time. Some of the main drivers for considering the use of a higher-voltage SEM — 50, 100 and 200 keV e-beam energy compared with classic CD-SEMs in the fab, generally operating at a cap of about 2 keV and much lower in most cases — have to do with damage to the top layer, which is being imaged. Photoresist is an example; 193 nm photoresist shrank as much as 20 nm in real time when exposed to e-beam. This made it difficult to do process control, because the operator was unsure whether he was measuring the unirradiated version or if it had been measured twice and now was beyond the control limits.

If a high-energy beam is used instead, high-energy electrons deposit next to no energy in the top layer because they pass right through it, whereas lower-energy electrons are completely absorbed, dumping all their energy into the top layer. If no energy is absorbed, there is no interaction or shrinkage. Also, a SEM's resolution is directly related to beam energy: The higher the energy, the shorter the wavelength and the better the resolution. Unlike the classic CD-SEM, which can be used on top of active devices, HVSEM's downside is that, when a 100 keV beam is shone on top of a transistor or even an interconnect layer, three or four (or more) layers separated from the transistor, there is the possibility that the transistor will be damaged. Intel irradiated devices through an entire metallization package. The chip had been completed, and they had test structures electrically characterized in terms of leakage and drive current. These were irradiated and characterized again, and it was determined that the device performance was degraded by as much as 10%. The degradation percentage is not as important as the fact that degradation itself occurred. Any device performance alteration is serious because it means the device has changed, and generally indicates the part is at higher risk to fail after usage. Sematech is currently attempting to establish an imaging irradiation threshold at which this would not happen. Since it is not a good idea to irradiate high-energy electrons that will make it to the sensitive device layer, it was concluded that HVSEMs cannot presently replace a CD-SEM.

The Intel study demonstrates that the metrology bar is constantly being raised. While undeniably useful, in this case the three-year span in the ITRS shows production is not the right target for generating capability on the scales depicted by the roadmap. Companies like Intel have already started evaluations with 22 nm node features. The aggressive numbers for post-gate etch feature sizes are not somewhere in the next decade; they are here today and metrology must address them.

The future is now.

1. B.J. Rice, H. Cao, M. Grumski and J. Roberts, "The Limits of Metrology," Intel Corp., March 2005.