The High-Speed, Low-Cost, Lead-Free Challenge for Flip-Chips

New requirements are driving new challenges for manufacturing small precision assemblies. Application-specific integrated circuits (ASICs) for high-speed applications, such as fiber-optic transceivers, generate a lot of heat that must be dissipated away from the IC for it to operate properly and reliably. Cost reductions are always critical for consumer products, and this article addresses the major cost drivers for flip-chip. Lead-free products are being required by the international community as part of the Restriction of Hazardous Substance (RoHS) policy,¹ which is more of a challenge for flexible circuit (flex) than FR4 boards. Some options will be discussed.
 
The comparison of electrical and thermal properties of various interconnect technologies are shown in Table 1 , along with some of the advantages and disadvantages.²

As noted in Table 1 , the electrical characteristics of flip-chip are better than surface-mount technology (SMT), chip on flex (COF) or micro ball grid arrays (µBGAs) because of lower inductance and capacitance. Flip-chip also has the lowest resistive path. The challenge of using flip-chip electrical advantages in very high-speed applications, such as 10 Gb/sec and higher fiber-optic transceivers, is to remove the heat from the IC.

Comparing the cross-sections of COF (Fig. 1) and FCOF (Fig. 2 ), you can see that the backside of the COF IC is mechanically and thermally connected to a metal stiffener. This is a very efficient heat sink. The backside of the flip-chip IC is in open air, and without very strong air movement, the IC will operate much hotter. The metal stiffener of the COF can easily be thermally attached to a next-level heat sink for further improvement.

One method of improving the thermal dissipation of FCOF has been evaluated, and the results can also apply from flip-chip to a printed circuit board (PCB). A "Bobbin" (Fig. 3 ) style heat sink was attached to the bare backside of the IC, using a 70% alumina-filled resin, and the ØjA was measured. The ØjA was reduced to 65°C/W from 74°C/W. Thermal vias can also reduce the thermal conductivity further.

1. The backside of the chip on flex (COF) IC is mechanically and thermally connected to a metal stiffener. This is a very efficient heat sink.

2. The backside of the flip-chip on flex (FCOF) IC is in open air, and without very strong air movement; the IC will operate much hotter than the COF shown in Fig. 1.

Cost reduction

One of the main cost drivers for flip-chip is the underfill process. Underfill is used between the IC and the substrate to absorb the difference in thermal expansion between the two.

3. The use of a bobbin-style heat sink significantly improves thermal conductivity.

Organic substrate base materials are formulated to have a thermal expansion, which closely matches the thermal expansion of the copper circuitry. This match prevents cracking, work-hardening and delaminating of the copper. Therefore, most organic substrates have a coefficient of thermal expansion (CTE) of 17-18 ppm increase in linear length per degree temperature change. A silicon IC has a CTE of 3.5 ppm. The underfill material is an epoxy that has an alumina filler mixed in to reduce the epoxy's CTE from ~65 to ~26 ppm. This epoxy helps to protect the IC from the environment while acting as a stress absorber. In effect, it is increasing the cross-sectional area of the interface dramatically. Without the epoxy underfill, the tiny solder bump might work-harden and crack. This paper will discuss three types of underfills: standard edge dispensed, no-flow and preflow (an IMI patented process) underfill.

The edge dispense underfill process relies on capillary action for the epoxy to wick under the IC, filling the gap. Typically, a very precise, fully automatic dispenser is used. The substrate is preheated to optimize the wicking, and the temperature is maintained after dispensing until the epoxy wicks are completely under the IC and come out the opposite side. The temperature, solder bump pattern and dispense pattern all affect the ability to achieve a void-free underfill. The epoxy is then cured in an oven or a conveyor furnace.

No-flow underfill integrates the IC pick-and-place/solder reflow operations with the underfill/epoxy cure operations. This saves on floor space, capital and labor and, if used, eliminates the need for nitrogen (N₂). Figure 4 compares the process flow of edge dispense to no-flow underfill.

4. Process flows of edge dispense vs. no-flow underfill are compared.

These no-flow underfill materials include the flux, required for solder bump reflow, with the epoxy resin, required for stress relief. The epoxy is applied before the IC is placed onto the substrate instead of after solder reflow (Fig. 5 ).

5. No-flow underfill materials include the flux and epoxy. The epoxy is applied before the IC is placed onto the substrate instead of after solder reflow.

Having the flux in the epoxy has many advantages. With the current process, the flux is applied to the solder bumps during the flip-chip operation. This slows down the pick-and-place machine and makes the pattern recognition more difficult. Because the preferred flux for SMT is very aggressive, it can be a reliability concern for the bare IC. Therefore, this flux is cleaned off the substrate prior to placing the flip-chip IC. If a less reactive flux is used, the solder reflow is performed in a N₂ atmosphere. A N₂ atmosphere can cause excessive solder wetting of the flip-chip solder when organic solderability preservatives (OSPs) are used. Besides the process trade-off of using N₂ or not, the cost and availability of implementing N₂ for reflow in the production environment needs to be evaluated as part of the overall process costs.

When using no-flow underfill, separate fluxing is not required, so the pick-and-place operation throughput may double. The epoxy is already under the IC and protects it from the more aggressive fluxes so N₂ is not required. The solder reflow operation may also cure the underfill epoxy, eliminating or reducing the need for a separate underfill cure.

The substrate may cost more, since some form of solder dam is required to control the solder wetting away from the solder joint or the IC can collapse and come into contact with the conductors on the substrate.

Preflow trades off the need for a solder dam on the substrate with the need to flux the bumps during pick-and-place. The gap is maintained so that yields and reliability are improved.

The infrastructure development required to support lead-free is similar to that required for transitioning from through-hole to SMT in the beginning of the '80s. Hundreds of component suppliers had to make the resistors, capacitors, coils, switches, connectors, ICs, etc., in both package types and configurations. Each process line was dedicated to one or the other, and if you had mixed technology, which most applications were for years, the boards went through each process separately.

With flexible circuits, the lead-free challenge is even greater than with FR4, because the adhesives used in the lamination process deteriorate at the elevated processing temperatures required by the leading alloy contenders. Table 2 identifies alloys that have potential for use on flex. When talking about lead-free flip-chip, you have all of the challenges of lead-free SMT with the added challenges of flip-chip. It was previously believed that the process line would need to be dedicated to lead-free or the product would have to be processed twice. We have developed a hybrid process that allows the use of lead-free SMT, along with eutectic flip-chip. Some of the hard disk drive manufacturers are leading this effort and working with a long list of suppliers to procure lead-free components. A lot of progress has been made with higher-temperature adhesives, although there are still limitations in the quality of the solder joint³ and the ability to remove the flux.

Using immersion silver might be a key to the successful processing of a lead-free product. It is more wettable than nickel or OSP, and doesn't have the potential embitterment concerns of gold. Another advantage of immersion silver is that it doesn't require a nickel underlayer like gold does. In flip-chip applications, electroless nickel and gold are used because it is difficult to get all of the traces shorted together for electroplating. Electroless nickel is higher stress, and thin traces can crack.

These and other advancements are in development in anticipation of the needs of applications requiring small precision assembly. Because of the interrelationship of all levels of interconnect involved in flip-chip, a joint effort is required to successfully implement almost any change.