Alers Visits Interconnect Reliability Concerns

Glenn Alers is principal engineer at Novellus Systems Inc. (San Jose), where he works on integration and reliability issues associated with copper/low-k dielectric interconnects. Prior to joining Novellus, Alers spent seven years as a member of the technical staff at Bell Laboratories (Murray Hill, N.J.), where he worked on reliability issues of silicon-based circuits, including electromigration, thin gate oxide reliability and high-k dielectrics. He holds a Ph.D. in physics from the University of Illinois (Urbana-Champaign).

SI: Can you bring us up to date on the most pressing interconnect reliability issues?

Alers: A few years ago, people were coming up on the learning curve with copper and low-k dielectric integration. People have worked through that burden, and now it's come to reliability and scaling. "How do you scale down the interconnects," and "How do you maintain yield and reliability?"

SI: How do copper/low-k issues compare with copper/SiO₂?

Alers: There are certain reliability issues that were not an issue for SiO₂, but are becoming a larger issue for low-k dielectrics. For example, time-dependent dielectric breakdown (TDDB) and ILD reliability. With very thin barriers and softer dielectrics and issues of absorption of water into the low-k films, adhesion and TDDB are more of a concern. Companies must now work to meet their 10-year lifetime specifications for the ILD.

SI: Is reliability affected by scaling?

Glenn Alers (Source: Novellus Systems)

Alers: We don't see any fundamental limits as far as scaling goes. Generally, as you decrease the size of a line, the current going through the line remains the same, which means current density increases. More margin is required for electromigration. But there are several ways to mediate this: one is capping layers, such as cobalt and tungsten capping layers; the other is an alloy of copper. But both come with an increase in the RC product of the line.

Capping layers can extend copper electromigration for many generations. The lifetime improvement there is one or two orders of magnitude. It is an electroless solution with the advantage that it's selective — so it doesn't require any additional patterning. But people are hesitant to add a new material to the back end. So if it can be avoided, it will — but maybe it can't.

The copper alloy is more of a one-generation or two-generation improvement, but it's fairly low-risk. I think you'll see people introducing copper alloys first and capping layers second.

SI: Are ALD barriers as reliable as PVD barriers?

Alers: No. The PVD copper/PVD tantalum interface is somewhat magical, and people don't want to give it up. Unfortunately, thermodynamically, you cannot deposit pure tantalum using ALD. There are certain precursors you can use that contain fluorine or halides, but they are not compatible with copper. With the metalorganic precursor, you incorporate carbon and nitrogen in the film, which degrades adhesion. But that's not going to stop ALD implementation, because it enables the barrier thickness to be scaled very dramatically. So right now, you need to deposit a pretty thick PVD layer to cover all parts in the feature. ALD provides perfect step coverage, so it can cover the small defects and imperfections at the bottom of the via. We are depositing roughly 300 Å in the field and hoping to get 50 Å in the bottom of the via. With ALD, we can deposit 60 Å Ta with PVD on top of 10 Å ALD TaN, which occupies less volume in the trench and lower line resistance than PVD TaN/PVD Ta.

SI: How soon might this approach be implemented?

Alers: I don't know. PVD continues to have a lot of steam left in it. There are other ALD approaches too. An additional ALD layer can be deposited between the ALD TaN and the PVD copper to improve adhesion to the copper and therefore improve electromigration. The ALD adhesion layer also enables the use of ALD copper for an all-ALD barrier/seed solution.

SI: What are the best ways of preventing reliability failures with respect to low-k dielectrics?

Alers: The biggest issue as we continue to scale the k of the dielectric is ILD reliability. Issues like water absorption, mechanical integrity and barrier integrity are the three big concerns.

SI: What about the next-generation low-k?

Alers: Nobody wants an incremental improvement because it's very painful to introduce a new dielectric. That means the dielectrics will be more exotic with more reliability concerns and risk. So I see the current generation of low-ks having quite a bit of staying power.

SI: Are there new testing methods?

Alers: A lot of testing methods that used to generate no failures now have failures, like temperature cycling and environmental testing. Temperature cycling during processing and operation cause differential thermal expansion of the copper relative to the dielectric. This induces mechanical stresses that can cause yield and reliability problems. As dimensions shrink, the stress gradients increase because the same amount of stress is confined in a reduced geometry. In addition, dielectric materials are getting softer, which are then more susceptible to failures.

For additional information on yield management, go to www.semiconductor.net/yield.