Subwavelength Imaging at k₁<0.3

In traditional semiconductor manufacturing, IC layout patterns are printed onto a silicon wafer using light projected through a mask or reticle. For earlier process technologies, the ratio of target resolution to optical resolution, measured at λ/n, has remained above or at least at unity. With newer process technologies, however, manufacturing engineers must create silicon structures at a resolution well below the wavelength of light used to project the IC layout pattern. In fact, with the 193 nm exposure equipment planned for leading-edge 65 nm technologies, engineers face the challenges of dealing with features printed at λ/3, with k₁ factors approaching 0.3 or even below. The 45 nm node will require us to print at λ/4 with k₁ right around 0.25 (Fig. 1 ).
 
Printing mask features below half or even down to a quarter of the optical exposure wavelength requires applying resolution enhancement techniques (RETs). This is true whether the pattern being printed is a clearfield polygate type or a darkfield contact/via type. While it may seem that there are several possible choices of RET, they are all doing basically the same thing. RETs alter the diffraction pattern that emanates from the object plane (i.e., the reticle) in such a manner that, when it is captured by the objective lens, the imaging of a desired target pattern is enhanced.

This is accomplished by properly engineering the illumination, the reticle pattern, the reticle phase and transmission, and the imaging lenses. This diffraction pattern engineering (or wavefront engineering) is necessary because of the continuing push to lower and lower k₁ values in manufacturing. But in low-k₁ imaging, all patterns are not created equal. So as a result of maximizing the imaging of one type of pattern, other pattern types suffer.

Today's advanced lithography for DRAM/ flash is already operating at k₁ ~0.3. The manufacturing for leading-edge logic devices does not follow too far behind. Patterning at the near theoretical lithography imaging limit (k₁ =0.25), even with hyper-NA (numerical aperture) optics, the attainable aerial image contrast is marginal at best for the critical feature. Thus, one of the key objectives for low-k₁ lithography is to ensure the printing performance of critical features for manufacturing. RET masks, in combination with hyper-NA and illumination optimization, are the optical extensions enabling lithography manufacturing at a very low k₁ factor.

1. With the use of 193 nm lithography planned for leading-edge 65 nm technology, and even on to 45 nm, the k1 factor continues to drive down toward the theoretical limit of 0.25.

There are four basic types of RET mask candidates for the 65 nm node — namely, the alternating phase-shift mask (altPSM), attenuated PSM (attPSM), chromeless phase lithography (CPL) PSM, and double dipole lithography (DDL) using a binary chrome mask. The wafer printing performances from CPL and DDL have proven that both are strong candidates for the 45 nm node.

The industry is clearly on a path to evaluate k₁<0.25 printing technologies, and since we seem to have pushed past the threshold of multiple exposures, 32 and 25 nm in optical extension are well within sight.

But (yes, there is always a "but") the use of strong RET masks calls for design for manufacturing (DFM) help from the EDA side. The varying RET schemes, a push for very restricted design rules, and the extremely high cost of lost productivity, time-to-market and mask cost itself, make a "pre-qualification" of RET during layout implementation a downright must. Whatever scheme chosen, design-enabled lithography simultaneous with lithography-enabled design has sent a wake-up call throughout the EDA industry, and we see many point tool suppliers emerging that address one issue or the other.

CPL: Of the four basic types of RET mask candidates for the 65 nm node, wafer printing performance demonstrated recently for CPL has proven it is a strong candidate — not just for 65 nm but also for the 45 nm node and likely beyond. One of the key technology features for CPL is the transmission control capability using "zebra" chrome patterns. The zebra patterns are plurals of chrome patches that are placed on the top of mesa phase features on the CPL mask (Fig. 2 ). Each individual chrome patch is not resolvable but collectively they act as halftone transmission control for the 100% transmission phase features.

2. The CPL PSM with chrome patch (left) is compared with the altPSM (right). The 3-D structure of lines/spaces are different on the reticle.

When patterning with high NA and off-axis illumination (OAI), CPL can achieve very high-resolution imaging that rivals the altPSM. It also has demonstrated an excellent printing resolution potential for critical feature pitch and CD. For zebra CPL, features as small as 28 nm have been printed in resist. In an early adoption example, it is feasible to apply CPL in a "gate shrink" design without using zebra for transmission tuning. Excellent gate CD control was observed for the printing of a logic device.

DDL: Double dipole lithography is an excellent alternative for 65 nm node manufacturing. Dipole illumination enhances printing resolution for the mask features with orientation that is favorable to the optimum dipole exposure. For the mask features with opposite (or unfavorable) orientation, dipole exposure produces little or no imaging contrast. As an example, for X-dipole, it enhances the printing for vertical (V) line features but suppresses imaging contrast for horizontal (H) features. This is true vice versa. By exploiting this unique printing behavior, it is possible to combine V and H masks with respective dipole exposure for each to achieve an overall printing performance that can match closely to the use of single-exposure PSM.

There are three critical steps to ensure a successful DDL mask set (V and H) generation. The first is the use of model-based pattern decomposition to separate the critical V and H components of any random two-dimensional mask pattern. Next is the design of optimized shielding for the corresponding critical features. The mask decomposition must optimize shielding width and shape for the unfavorable dipole exposure in order to warrant a robust critical feature printing performance from the favorable dipole exposure. Last but not least is the application of scattering bars (SBs) for optical proximity correction (OPC) on the critical features. SBs provide necessary protection for isolated feature edges to get the full benefit of dipole exposure. It is fair to say that, without SB OPC, the chance for a DDL technology to succeed is very slim.

SRAFs: The use of rule-based SBs for all types of masks has become the de facto OPC standard since the 180 nm node. For the upcoming 65 nm node, SB OPC is very important. Unfortunately, because of the preferred use of 4× magnification, and based on the design knowledge accumulated for the existing OPC scheme, the SB feature width in a 4× reticle can become smaller than the ArF exposure wavelength. With excellent progress in recent years for the maskmaking process technology, most of the merchant mask shops today have demonstrated superb capability to build and deliver well-made SB OPC masks. Still, the CD specification requirement for sub-exposure wavelength SB structures adds substantial cost to the mask set. Going forward, the SB mask specifications can only get stricter. We expect that 4× masks will become much more challenging to build for higher-NA exposure with or without immersion.

The only alternative that seems to be reasonable is to not design with sub-resolution SB OPC, but with one that has large enough and printable size (the larger SB can be much more effective in assisting high-NA imaging performance). This will allow SB features that are more or less in the same CD range for the critical mask features. The unwanted SB residue can be easily erased with second SB trim exposure. The trade-off for a more manufacturable mask is the two-exposure scheme as suggested here. Another supporting argument for the second trim exposure is the need to remove possible sidelobe residue. This concern calls for a DFM tool, as already mentioned, to capture any possible printing residues at post-OPC in a model-based silicon lithography checker, so that both mask and wafer yield can be better assured.

In a new approach, a model-based SB OPC method derived from interference mapping lithography (IML) has shown impressive printing results for both clear (gate) and darkfield (contact and via) mask types.

The IC manufacturing industry has become more and more receptive to the idea of a second exposure, which opens up a wide range of possibilities for better imaging at an extreme k₁ factor. This is not just limited to the necessary second SB and sidelobe trim exposure, but it would become feasible to achieve more resolution enhancement. The final frontier scenario as shown in Figure 1 is likely, once again, to be extended.

The argument against a double-exposure scheme is not new — the scheme will penalize wafer throughput, with a seemingly increased mask set cost. Nevertheless, the incentive for a less challenging but better lithography under an extreme low-k₁ factor is very strong. In addition to the necessary SB and sidelobe trimming, the second exposure may be designed to achieve a print resolution beyond the k₁ =0.25 barrier. In fact, by splitting the very tight-pitched features into two less demanding pitch masks, each mask can have a more relaxed k₁ factor. We can reduce the maskmaking requirements and cost with less stringent specifications for both masks. Moreover, making full-sized SB OPC masks should be easier to deal with in all aspects.

Looking ahead, for manufacturing at 45 and 32 nm nodes, we must find a way to achieve the desired imaging contrast for manufacturing with full-sized SB OPC under hyper-NA immersion. One strong motivation is to find ways to break through the so-called k₁ barrier (0.25). Multiple-exposure schemes are well-suited for this task.

Interference Mapping Technology (IMT) is an innovative method by which a full-pitch range of deep subwavelength reticle patterns can be defined based on any illumination condition, including highly coherent on-axis and strong off-axis illuminations. Using this method, reticle features that do not print on the wafer can be added to the target pattern, which will enhance the aerial image of the intended target pattern, resulting in higher-resolution imaging and larger process latitudes.

This method can be used for binary reticles, attPSMs and other PSMs. The concept behind IMT involves mapping the interaction between each point in the field with all the target geometry that is within the optical range of influence around that point. Using IMT expands the concept of scattering bars and anti-scattering bars to a novel concept encompassing the employment of features on the reticle that are actually not sub-resolution. In this example, the "assisting features" are actually larger than the target contact, but they are non-printing.

For earlier process technologies, traditional methods have been successful without requiring any adjustments in the design phase. In fact, the semiconductor industry has until now considered that the business benefits of hiding the complexity of lithography corrections outweighed the potential benefits of involving IC designers in lithographic optimization.

To deal with sub-90 nm processes, however, that consideration has been reversed. In fact, the traditional goal of implementing RETs without involving the design community prevents use of more sophisticated RETs that cannot otherwise be applied to an existing design. CAD layout engineers have seen design rules exploding and, for a 90 nm process, we typically see a 4-5× rise in the number of rules, many of which are never explained to a designer if they are related to lithography, etch, CMP, other manufacturing needs, or all of the above.

At the 65 nm node, the previously discussed resolution problems of low-k₁ lithography alter traditional priorities, by necessity elevating the awareness of advanced lithography requirements in the design phase. Without careful attention to these concerns prior to tapeout, semiconductor manufacturers will face costly added design iterations. With mask costs exceeding $1M for advanced processes, additional iterations mean significantly increased direct costs to any device they want to bring to the market. Perhaps worse, significant delivery delays associated with design iterations mean reduced market share and lost revenue as product life cycles shrink in today's competitive environment.

At the same time, newer methods for subwavelength lithography in nanometer-scale ICs need greater flexibility for applying different methodologies across a single design. 65 nm ICs will require optimized multiple-RET for all critical mask levels, including strong phase shifting, and model- and rule-based OPC for most of the other layers. Multiple RETs applied in varying degrees on different layers depending on feature type and polarity requires much greater collaboration between design and lithography to achieve optimum results in the shortest possible time. As the foundation for this new approach, the emergence of design-enabled lithography methods and lithography-enabled design tools promises to help reduce cost, complexity and turnaround time for development of increasingly advanced ICs.

Newer OPC methods combine the benefits of traditional rule-based OPC with model-based methods. To control excessive run times and data explosion, several steps can be taken: hybrid techniques between rule- and model-based OPC allow engineers to trade off ultimate accuracy for conversion speed. Combined with methods that take advantage of hierarchy in tapeout data, this approach permits efficient full-chip correction.

Using information embedded in the incoming data stream, design-aware processing promises to limit increasingly long RET run times and help optimize key design structures so different RET approaches can be selectively applied to more critical regions of a design. Design criticality needs to be annotated in the cell/block creation step, and RETs tailored toward achieving the feature-level compensation and control that is needed to successfully build a full-yielding device (Fig. 3 ).

3. Design-aware processing promises to limit increasingly long RET run times and help optimize key design structures.

At a more fundamental level, however, an emerging class of lithography-aware design tools allows designers to apply more proactive methods to ensure compliance with downstream lithographic requirements. Using sophisticated design rule sets that encode lithographic constraints, these tools allow designers to identify and correct problematic structures well before tapeout.

The lithography process needs to know of these criticalities, and receive an automated feed into its pattern analysis tools to optimize the printing conditions — illumination, NA, sigma — of a particular pattern and, most of all, the process window match of all the varying critical patterns in a design. Low contrast or low-image log slope areas need to be flagged for careful analysis throughout the process window. If necessary, these areas need to be fed back to the designers for further improvement of the layout and design styles. In many cases, by identifying "weak" spots in a layout cell/block, libraries can be updated with a more lithography-compliant and manufacturable design style, thereby preventing many reoccurrences of some of the same problems. Catching these "weak" spots at the cell creation step will save many months of post-tapeout tweaks and post-layout design fixes.

With the availability of flexible data models such as the OpenAccess model standard, designers will eventually be able to embed design information in manufacturing data, permitting downstream tools to optimize analysis on structures that are critical to the design.

With conventional tools, designers would need to wait for manufacturing to determine if the design contained any forbidden pitches or complex structures that complicated RETs. Integrated in existing design flows, these lithography-aware design tools allow engineers to design for OPC, RET or even PSM compliance. As designers create edges and place shapes, such tools provide immediate feedback to ensure that the layout will not violate subsequent OPC or phase-shifting requirements.

Along with tools for RET-compliant cell and block creation, advanced physical design tools help ensure that placement and routing proceed without introducing additional lithographic complications. The use model is typically in an interactive way on a cell or block macro level, with continued checks for RET compliance. Cells will be interactively checked, and batched off into "golden" libraries. At the time of block or chip assembly, a full-chip batch process is used to run a final sign-off verification.

With this type of enhanced flow, designers can proceed to final tapeout, confident that the resulting manufacturing data is fully compliant with downstream lithography requirements. The industry has long been concerned about the ever increasing productivity gap that designers are facing due to some of the inefficiencies of their tool sets. In this new flow paradigm, increased productivity is guaranteed through a near zero failure rate at tapeout. No costly redesigns are required for manufacturing rule violations, no masks are lost due to erroneous data, and time-to-market requirements are being met by a right-the-first-time approach (Fig. 4 ).

4. A fully integrated pre-tapeout design flow minimizes costly redesigns and masks lost to erroneous data.

Conclusion

For RET masks to be prepared for manufacturing in the optical final frontier with multiple exposure schemes, several enabling technologies on the hardware/ modeling side are essential:

• Resist process calibration that takes into account the detailed illumination effect, for both simulation and model OPC purposes.
• Illumination pupil optimization for each of the exposure masks.
• Source and mask optimization (SMO).
• Model-based SB OPC for contact and gate masks.

Model OPC calibration requires not only a good illumination model, but also the use of true 2-D structures to realistically fit the model OPC calibration. Furthermore, the accuracy of the model is greatly dependent on the input data. Typically, hundreds to thousands of measurements are needed, and CD-SEMs only allow 1-D measurements on a feature at a time. A more advanced calibration methodology employs 2-D digital imagery, which, since it takes all the feature contours into account, guarantees higher model accuracy with far less involvement in the calibration. We will discuss this patented approach at some other point in time.

Illumination pupil optimization is a powerful way to improve overlapped process windows for various feature types and to enhance the line-end printing. A strong and fast simulator is needed, with an auto-calibration routine that allows the user to optimize SMO in an efficient and automated mode.

On the design side, the emergence of tools and methods that break down traditional boundaries between design and lithography allow us to achieve optimum results in the shortest possible time. The continued evolution of design-enabled lithography and lithography-enabled design capabilities promises to offer increasingly effective strategies for ensuring manufacturability of more complex ICs.

These enabling technologies for multiple-exposure RET masks allow for the prediction that multiple-exposure RET masks can get us to 32 nm and beyond. Does anyone else hear 15 nm?