Not All RETs Are Created Equal

As linewidths continue to scale, the industry continually evaluates how best to get the sizes and performance needed. Reducing the wavelength of light — whether through tricks like immersion lithography or through source changes like EUV lithography — is one way to get there, but chipmakers will first try to get everything they can out of their existing photolithography tools.

Freescale Semiconductor (Austin, Texas) and Photronics Inc. (Brookfield, Conn.) announced recently some results from their ongoing joint research into resolution enhancement techniques (RETs), which let users get more out of conventional tools than they would with standard binary masks. The chipmaker and maskmaker have been working together for close to two years, with a formal agreement in place since December 2004, to jointly explore the various approaches for preparing leading-edge reticles for 65 nm and below semiconductor manufacturing.

The idea behind the studies is to figure out the best method to extend the life of current-generation optical lithography tools. Freescale supplies representative patterns and analytical support, wafer imaging and data analysis, and Photronics supplies test reticles and reticle fabrication details. Goals of the study include assessing the technical and commercial merit of various RET approaches, optimizing reticle fabrication techniques and defining tolerances, and determining overall RET manufacturability.

"We're very interested here in critical dimension control across the die, but particularly for our high-performance portfolio," said Joe Mogab, senior technical fellow and director of the Advanced Products Research and Development Laboratory at Freescale. Freescale's focus in on random logic. "Gate length is the be all and end all; from a uniformity point of view, it's a big deal."

The researchers set out to compare RETs — namely, 6% attenuated phase-shift masks (attPSMs), complementary PSMs (CPSMs) and chromeless phase lithography (CPL) — to figure out which have the attributes that will best suit Freescale's needs for the 65 nm node. "These are all contenders, because on paper they all look pretty good," Mogab said. But after a great deal of quantitative work (literally thousands and thousands of CD measurements, Mogab said), the researchers were able to discern some differences.

Although they found little statistical differences between the methods with respect to CD control achieved at the 65 nm node, they did find significant differences in other important metrics such as line-edge roughness (LER) and 2-D image acuity. Overall, the study looks at a particular technique's manufacturing worthiness. "It's a comparison not only of technical performance, but also the relative readiness of approaches," explained Scott Hector, Freescale's advanced lithography manager. Considered along with the technical data, for example, is the maturity of the approach, which is important for infrastructure concerns such as tools for repair and the ability to convert design data to mask data, Hector added. There were also cost considerations.

At least at the 65 nm level, the attPSM appears to offer the best attributes when considering all the criteria. "It provides adequate control, gets us to where we want to be, and has the maturity to make us feel comfortable," Mogab said. Of the three approaches, it is the most mature, giving it better reproducibility and reliability, he added. "And it's probably the least complicated from an EDA and design point of view." Hector added, "It's considerably less complex than the CPSM or CPL technology."

Some three to four years ago, blank technology was a significant limiter to the 6% attPSM, Hector noted. But suppliers have improved their performance, and the blanks now have a lower defect density at a reasonable cost. At the same time, blanks for hard phase-shifting masks (CPSM and CPL fall into this category) are much less expensive because they are essentially binary mask blanks, Hector said. "But the process for fabricating the masks is less widely used, and inspection is more difficult."

Hard phase shifting also provides better image performance, Hector said, noting that CPSM provided the best, then CPL. "But when put into practice, they didn't provide a significant enough difference to warrant using them at this point." One drawback, for example, is that CPSM requires two reticles to print a single layer, causing a major hit in exposure tool throughput, Mogab said.

Of course, another chipmaker might weigh the factors differently, depending on its products or manufacturing needs. A very high-margin chip, for example, might be able to handle higher reticle costs. And a memory maker might have a very different approach. Because random logic does not have repetitive features across the die, there tend to be more "gotchas," Mogab said, noting that this made the EDA software maturity for a given technique particularly important for Freescale. This is one factor making hard phase-shifting options more challenging at this point.

So the answer could change over time. As CPSM and CPL techniques become more mature, Mogab noted, they might gain in feasibility. In its continued collaboration, which is a three-year commitment, the researchers now plan to move ahead with 45 nm exploration. In addition to running through similar tests that were done for 65 nm production, the researchers will be considering some factors differently because of the changes that go along with a node change. For example, they will certainly be more focused on LER, Mogab said, a growing challenge as linewidths scale down.

For more additional information on lithography, go to www.semiconductor.net/lithography.