Tools of the Trade for Backside FA

Die size reduction has led to the increasing placement of active circuitry underneath the bond pads without the use of additional reinforcement layers. This so-called circuit-under-pad (CUP) structure, in combination with multiple levels of copper and low-k dielectrics, brings additional challenges for electrical defect localization and physical failure analysis (FA). In this case, backside FA can be more easily carried out than frontside FA, using a combination of reactive ion etch (RIE), parallel polishing, CMP, wet chemical etching, focused ion beam (FIB) and SEM techniques. Huixian Wu and coworkers at Agere Systems (Allentown, Pa.) recently reported on the use of various methods to effectively address reliability issues in five case studies presented at the recent International Reliability Physics Symposium in San Jose.

CMP and thermal anneals impart significant strain energy during wafer fabrication. This strain energy is exacerbated during package assembly processes, including wafer dicing, wire bonding, flip-chip die attach, overmolding of leadframe devices and underfilling of flip-chip devices. The combined strained energy can lead to delamination or cracking, often brought out during reliability stress testing.

In the CUP design, because the gold balls reside on top of the bond pads and block thermal and light emission from defect sites, backside defect localization is more feasible. Also, traditional wet chemicals used for gold ball removal will etch copper interconnects and barriers. Parallel polishing of gold balls can cause cracks or delamination. Deprocessing of copper and low-k materials using RIE must be balanced to optimize etch selectivity, and prevent RIE grass and surface roughness.

There are three major steps involved in backside FA processing: backside sample preparation, backside defect localization and backside physical analysis.

In this study, Agere engineers used a combination of mechanical milling (using Chip Unzip by Hypervision Inc ., Fremont, Calif.) and RIE for silicon thinning of a plastic BGA down to ~100 µm of silicon. They used a backside fluorescent microthermal imaging (FMI) technique to localize defects during unpowered pin-to-pin curve tracing. The same thermal emission was detected using liquid crystal analysis through the backside of the die.

Removal of the silicon die from the surrounding package was accomplished using RIE and parallel polishing (to ~5 µm silicon). Then, 20% TMAH etching at 70°C selectively removed silicon from the gate oxide with good across-the-die uniformity and control of backside deprocessing. Physical FA at the gate level can reveal a number of potential defects, including soft breakdown of ultrathin oxides, stress-induced leakage current, trap-assisted tunneling, etc.

CMP, RIE and wet chemical etching in a manner similar to frontside FA enabled backside metal-level deprocessing. Multistep CMP with different polishing conditions (slurry chemistry, pad type, pressure or rotation speed) can optimize the polishing results.

The interface between the copper barrier and dielectric is susceptible to debonding in a similar manner to stress corrosion cracking. Moisture can also have a pronounced effect on reducing interface adhesion.

With respect to low-k dielectrics, weak mechanical properties and poor adhesion contribute to cracking and interface adhesion failures. The primary failure mode in structures with a high breakdown field has been mechanical failure of the dielectric barrier or delamination at the barrier/ILD interface. The failure mode has been found to be strongly related to process conditions and, interestingly, not necessarily a function of stress test conditions.

In case study #1, no gate-level defect was found, but backside FMI isolated a defect, later shown by SEM to be electrical overstress (EOS) damage to the copper at Metal 5. In case #2, again, no gate-level defect was found, but a thermal emission anomaly was observed upon deprocessing to M5 and M6. SEM analysis showed cracks in the metal. In case study #3, CMP deprocessing revealed an anomaly at M4 and M5. Similarly, in case study #4, optical images showed an anomaly at M4 and M5 after CMP and chemical etching. A SEM image at the edge of the meander/comb structure showed die cracks, copper extrusion and copper voids, believed to be caused by EOS. In case study #5, damage was found at the edge of the meander structure at the M5 layer using optical imaging. FIB cross-section/SEM showed die cracks and copper migration along the cracks. The damage was likely caused by EOS-induced thermal effects.

For additional information on yield management, go to www.semiconductor.net/yield.