Work Continues on Silicon Substrates

Since the beginning of flip-chip technology, people have examined the use of silicon as a package substrate, in part because the substrate's coefficient of thermal expansion (CTE) is exactly matched to the die.¹ Silicon is currently being used as a system-in-package (SiP) substrate material because fine-pitch interconnections are easy to fabricate on it.² Researchers at Dai Nippon Printing (Chiba, Japan) and Worldwide Electronic Integrated Substrate Technology (Weisti, Chiba, Japan) recently presented the results of their work on silicon substrates with through-holes at the Electronic Circuits World Convention.

Lately, silicon has been used mostly to implement high-density interconnection between die in an SiP, where the connection density to the circuit board was not necessarily very high. Through-holes would extend the usefulness of silicon substrates to include high interconnection density with the circuit board. In the next five years, BGA ball pitches are expected to be <200 µm. Organics might be able to handle ball pitches this low, but there is no question that silicon can handle them.

In addition to high interconnection density, package substrates also need to support high signal speeds. On-chip clock speed requirements are going from a few gigahertz to several gigahertz, and chip-to-board speed requirements are tracking the on-chip requirements closely. As a dielectric material, silicon does not have much of an advantage over organics, but its dimensional stability makes silicon attractive because interconnects and other structures can behave more predictably while in use.

In the work presented, silicon was used only as an interposer for an SiP. A multilayer copper/BCB interconnect structure was built on top of the silicon, and the through-holes were used only to provide area-array connections to the board (Figure ). The top layers used 5 µm lines and spaces and 20 µm vias with 30 µm lands. The through-hole diameters were 10-300 µm, and the silicon thickness was 170-300 µm. The combination of 10 µm diameter and 170 µm depth was among those featured.

A silicon SiP substrate can support high-speed, high-density interconnection between the chip and board.

Two methods were used to make the through-holes. In both cases, the holes were made using an inductively coupled reactive ion etch (ICP-RIE) process, and backgrinding was done to expose the through-holes from the other side. In one process, this was all done before the copper plugs were formed, and in the other, the copper plugs were made before the backgrinding step.

In both cases, the silicon was thermally oxidized (800 nm) after the holes were etched, and a TiN adhesion layer (30 nm) was deposited using metal-organic chemical vapor deposition (MOCVD). In the case where the backgrinding was performed prior to plug formation, the plugs were made by electroplating the copper onto the TiN barrier. In the other case, a copper seed was deposited prior to electroplating. In the case where the plugs were formed prior to backgrinding, some voiding occurred.

Thermal-cycle tests and temperature-humidity-bias tests indicated that the substrates were sufficiently reliable, provided that the TiN barrier layer was used. Electrical tests on the top layers were typical for the Cu/BCB combination, demonstrating capabilities well beyond 10 GHz.

One of the issues held against the use of silicon as a substrate material is the perceived waste of valuable silicon real estate. This is really not an issue, because most of the "value" of the silicon real estate is determined by what is made on it. The cost of the silicon in a leading-edge IC is small compared to that of the interconnect structures built on it. The cost of using silicon as a substrate should be compared to the cost of using other materials for the same application. From this view, using silicon is attractive for upcoming speed and interconnection density requirements.

Another possibility that has been talked about for years is the fabrication of simple power conditioning circuitry on a silicon substrate. Though it was not posed in this paper, placing power conditioning circuitry on a SiP substrate is a possibility that must be considered as supply voltages continue to drop and peak currents continue to increase. Making this circuitry in the substrate material itself may soon be an attractive option.

One other possible application for through-holes in silicon is 3-D ICs. People have been looking at it recently, though it has only appeared in a few applications, and only in one commercial application. One of its many concerns is the formation of through-holes in product die. If sufficient work is done with silicon interposers, there may be enough confidence in the process for more people to try 3-D ICs.

Using silicon as a package substrate material is not only a viable possibility for high-speed, high-density packaging applications, it is an attractive one. As we get closer to the limits of CMOS's capabilities, the industry must consider such alternatives.

For additional information on semiconductor packaging, go to www.semiconductor.net/packaging.