Modeling Interconnect Variation — Optional or Mandatory?

With the adoption of copper interconnects at the 130 nm process node, the benefits of a faster conductor were tempered by the challenges of planarizing a softer material. Minimizing pattern-dependent copper and oxide thickness variation has become critical to meeting the increasingly stringent electrical requirements. Manufacturers and equipment suppliers responded with multistep polishing processes, selective slurries and advanced dummy fill/slotting techniques that minimized the thickness variation. At the same time, newer process nodes have created additional variation challenges as lines became narrower, additional metal layers were added and thickness metrology equipment began losing ground.

Understanding interconnect thickness variation at the latest process nodes has many benefits: Processes can be optimized, consumable selection can be improved, dummy fill/slotting algorithms can be improved and guard bands provided to design teams can be minimized. Traditionally, these tasks have been performed by running a set (or numerous sets) of test or characterization wafers. The resources (people, money and time) to do this increase exponentially with each node, while the need to explore new alternatives is also increasing.

We propose a new physics-based interconnect thickness modeling methodology to address a number of these issues. The methodology characterizes a process by combining the physics of deposition, polishing and consumables with data taken from characterization wafers. Once characterized, the resulting "virtual process" can be used to quickly and accurately predict the manufactured thickness of any design or test wafer, allowing manufacturers to derive all the benefits described above within hours, rather than the weeks previously required.

Manufacturers have made progress on a number of fronts to minimize copper-interconnect thickness variation as they move to new process nodes. These include multiple polishing steps, new slurries and pads, lower-pressure polishing, automatic endpoint detection, etc. Despite these significant improvements, the challenge of interconnect variation continues to increase.

One of the primary reasons is the decreasing size of interconnect cross-section with each new process node (Fig. 1 ). Going from 90 to 65 nm decreases the cross-section by 50%, which results in a 100% increase in resistance for the same line lengths. The decrease in cross-sectional area similarly impacts the effects of process-induced thickness variation and width variation. For instance, a damascene process that produces a 15% variation in minimum feature thickness at 90 nm would similarly produce a 20% variation in the minimum feature thickness at 65 nm if the absolute thickness variation remained the same.

1. From the 90 nm to the 65 nm node, interconnect cross-sectional area is reduced by 50%, resulting in a 100% increase in resistance for a line of the same length.

Each new manufacturing process improvement introduces the challenge of determining the success criteria and, specifically, how success or failure will be measured. The current interconnect technology for copper typically needs to be characterized with respect to three different parameters on three different types of measurement tools: copper thickness (e.g., MetaPULSE); surface height, such as dishing and erosion (e.g., high-resolution profilometer [HRP]); and dielectric thickness (e.g., UV-1280). These measurement tools are widely used in both development and manufacturing environments.

Each of these non-destructive tools has limitations in measuring submicron features (e.g., the tip size or radius of curvature of the probe). The more accurate metrology tools, such as SEMs and focused ion beam (FIB) systems, are more time-consuming, which adds significantly to processing costs. The SEM uses electrons to show magnified images of dielectrics and copper (Fig. 2 ), and similarly, a FIB uses finely focused ions that have an ability to sputter or cut through a material, allowing a sidewall image to be seen. SEMs and FIBs provide the necessary accuracy requirement (~5 nm imaging resolution), but are destructive and significantly more time-consuming and expensive than optical techniques.

2. SEMs are among the most accurate metrology tools, offering ~5 nm resolution.

Even if all the above measurement methodologies and resources are available, determining where to measure is exceedingly difficult. For this reason, almost all measurements are taken in the scribe line, despite the fact that most of the interesting variation occurs within the die. Many process improvements will not be implemented because of insufficient time and resources to validate them.

Perhaps the most important ingredient of identifying improvements is the ability to quickly explore alternatives. There are too many variables to test for optimal alternatives. Even the most experienced process engineers will not have enough time to anticipate expected results and define and execute experiments to test those results. Results should also be physically validated on test wafers, as well as multiple product wafers.

A fundamental question that provides nightmares for process engineers is, "What is the manufacturing variation?" A slightly more tractable problem is to quantify the systematic vs. random variation. Assuming that an answer exists to the latter question, the conundrum wrapped in the riddle becomes identifying the occurrences and sources of variation. Is the variation within-die, within-wafer, wafer-to-wafer, lot-to-lot or fab-to-fab? Is the source of the variation lithography or plating or CMP or etch? Answering these questions is a daunting task today and a nightmare for future processes. Manufacturing trial and error is a losing proposition.

Chip designers and manufacturers have adopted the use of dummy fill and line slotting to create a uniform interconnect layout pattern that theoretically minimizes topographical variation (and therefore the electrical variation of the interconnect). Design rules for dummy fill and slotting are created that specify the fill characteristics and locations. The impact of dummy fill on interconnect topography is difficult to measure for the same reasons indicated previously, and the resulting impact on delay and cross-talk is even more challenging to quantify. The current practice of creating design rules (typically density, linewidth and line space) that minimize the thickness variation is becoming more questionable with each new process node. A more sophisticated approach is required that goes beyond design rules.

The increasing number of transistors and gates that can be designed on a die brings a proportional increase in the requirements to connect those devices. This has led to an increase in the number of interconnect layers of up to 8-10 for 90 nm nodes, with more levels to come. These layers add an additional level of complexity, because the topology of each successive metal (and via) layer becomes the starting point for the next layer (Fig. 3 ). Even the pre-copper layers (STI and tungsten) have to be taken into consideration, since they are the starting topology for the copper levels.

3. Each deposition, etch, CMP and plating step impacts planarization at every metal and via level, which makes across-wafer planarity increasingly difficult.

Current progress

Modeling the interconnect manufacturing process is clearly required to deal with the increasing complexity of the deposition and polishing steps. A variety of approaches are being used to address this difficult challenge today (Fig. 4 ). Typically, the process-modeling group will create an equation-based model by fitting empirical data gathered from a designated number of test wafers. This technique has limited scalability, since the number of variables required to adequately capture the behavior is large and the interaction of the variables is becoming more complicated.

4. The key advantage of recent physics-based models is the expeditious nature of the calculation and its accuracy.

Another approach involves creating a model of the physics of the plating and CMP process. Although extremely accurate, the complexity of a pure physics model is beyond the reach of existing computing power. The most popular approach today for communicating interconnect manufacturing variation to designers is to develop a series of design rules based on a given process. New designs are then constrained to be within these specifications (typically, local density or linewidth constraints). The design rules also contain significant guard bands (best-case and worstcase thickness) to make them universal, but result in a significant loss in potential electrical performance and/or increase in power consumption.

A recently developed technology that uses physics-based modeling holds great promise. This approach is able to characterize a specific manufacturing process and accurately predict the copper and oxide thickness of any net or area on the chip. The technology takes advantage of the tight correlation of layout patterns to deposition and polishing behavior, which determines interconnect dishing and erosion. This proposed method uses a physics-based model combined with empirical results when appropriate.

The power of this methodology is that, once the model is calibrated for a process (e.g., ECD and CMP), using measurements from test wafers, it can be applied to other product layouts to obtain a full-chip thickness prediction. The model is based on the Preston's equation and contact-wear mechanics to relate material removal rate to pressure, velocity and layout pattern factors. By accounting for layout patterns of a chip and their subsequent influence on processing in thickness variability, the model can be used to predict thickness variation for any layout.

The flow of the proposed method consists of two steps: calibration and prediction (Fig. 5 ). As the name suggests, during the calibration step, the model is calibrated based on the thickness measurement data taken from ECD and CMP processes using a test wafer and the layout geometry extracted from the same test wafer. Once a model is calibrated, an "ECD/CMP Virtual Manufacturing Process (VMP) Library" is created, which is then used in the prediction step. In this step, the VMP library is used with extracted layout geometry from a product design for a full-chip prediction of thickness variation. Then a topographical analysis can be performed, such as identifying the high and low spots of a product chip and selecting those as measurement points.

5. The model is first calibrated based on ECD and CMP thickness data from test wafers and the layout geometry; the library then uses that information and the product design to perform full-chip thickness prediction.

The critical issue for the integration and process engineers is the accuracy of interconnect modeling. The physics-based modeling approach has been successfully used on multiple 90 nm product designs with >90% accuracy. The accuracy refers to 90% of variation (e.g., 200 Å variation on 3000 Å line means within 20 Å), not 90% of total thickness.

Physics-based modeling allows a wide range of applications that are too numerous to delineate in this article. Two specific applications are discussed in more detail, but the following applications are also possible:

• A new methodology to communicate interconnect thickness to designers who can extract realistic resistance and capacitance values instead of overly conservative guard-banded tech files.
• Process optimization.
• Design screening.
• Scientific design rule exception granting.

As described earlier, it would be extremely difficult and costly to implement an optimal dummy fill strategy by actually designing multiple layouts, and then processing and measuring wafers to characterize the effectiveness of different types of dummy fills on a variety of product designs.

The model-based approach allows engineers to examine various dummy features (e.g., shapes, sizes and amount) by simulating a thickness map for each type of dummy fill without actually having to process wafers. A test case (Fig. 6 ) shows a thickness variation map of a baseline process and an optimized process with respective distributions of thickness. Needless to say, a dummy fill decision made on an accurate prediction of topography helps enable the right decision to improve yield and circuit performance. This example indicates the promise of a comprehensive solution for managing copper variability, and its impact for maximizing performance and minimizing power.

6. Example of simulation of a thickness map for each type of dummy feature to determine an optimal dummy fill strategy.

Solutions for generating "intelligent" (as opposed to purely rule-driven) dummy fill based on topology (or, more typically, a proxy for topology such as density) are starting to emerge. Some of these "intelligent" dummy fill programs take the impact of capacitance into account as well. The most advanced intelligent dummy fill combines:

1. An array of algorithmic strategies (dummy shape, sizing and spacing, symmetric and asymmetric configuration, variable buffer distances).
2. More accurate prediction of the actual interconnect thickness (density models, empirical models, physics-based models).
3. Incorporation of the capacitance impact on the design (simple equation, 2-D/3-D extraction).

The CMP step is the second highest cost in the manufacturing process (21% for 90 nm), and the cost of consumables is 80% of that step. A fundamental question that every process engineer has to answer is, "How good do the consumables have to be?" The only way to answer that question today is to run a set of test wafers using two different consumable sets and measure the results. We already know how difficult the measurement process is. And, of course, each consumable set has a different optimal deposition and polishing time that would also have to be identified through additional manufacturing and metrology steps. Needless to say, the feasibility of exploring consumable alternatives rigorously is very questionable.

The best way to answer this question is through virtual manufacturing. Since accuracy is paramount, a physics-based model is an excellent alternative. We virtually manufactured two alternative consumable sets (Virtual Manufacturing Process [VRP] A and B) and compared them against the process of record (POR), a process that took hours instead of weeks or months by traditional means (Fig. 7 ). The analysis can also be performed across a range of product types using only the design file for those chips.

7. Modeling shows the process of record (POR) leads to greater dishing, erosion and copper loss than CMP with either of the two slurry alternatives.

Summary

The requirement for a model that can accurately and robustly represent interconnect manufacturing variation is becoming critical. The resources and time required to do this through trial and error have thwarted the efforts of process engineers to explore alternatives that can optimize their increasingly complex process. A new physics-based modeling technology offers a ray of hope. Process engineers can virtually manufacture a variety of test and product chips to explore a wide range of manufacturing applications, as well as to provide a new paradigm for communicating as-manufactured information to design teams.