FEOL Cleaning Challenges

Currently, there is considerable discussion in the semiconductor industry about the multitude of challenges facing wet processing in the front end of the line (FEOL). There is typically a tightening of specification limits for parameters that accompany a new technology node. There is increasing anxiety toward FEOL wet processing, however, because there are no effective solutions presently identified to address the anticipated cleaning challenges in this sector of the manufacturing cycle.

The standard in the industry for the removal of particles and residues has been to process wafers in batches by immersing them in a wet bench containing the appropriate chemistry. Typically, the particle removal is enhanced by the use of megasonic energy. These large and cumbersome systems have dominated FEOL and BEOL wet surface preparation, but their effectiveness for the future is now in question. At 45 nm and below, the required specification limits are likely to surpass the cleaning abilities of existing technologies, including batch. For example, the specifications for the 45 nm node proposed by the 2004 ITRS call for defectivity levels of <86 total particles at a size of 22.5 nm, all with a maximum silicon or oxide loss of <0.04 nm for each cleaning pass. These are particularly difficult targets, given that the cleans must be non-damaging to delicate features, such as polysilicon lines as small as 18 nm, and be performed on device structures with aspect ratios in excess of 5:1. This requires extremely controlled, highly selective cleans that many feel might not be possible with existing technologies.

Particle removal efficiency (PRE) has been the main driver for the use of megasonics in FEOL critical cleans. At 45 nm, an 18 nm polysilicon line will be extremely delicate, and an uncontrolled megasonic approach will not work. Indeed, even at the 90 nm node, customers have reported that FEOL structures cannot tolerate the use of megasonic power. Clearly, if megasonics are to be useful for emerging technology nodes, there must be a better understanding of how megasonic technology really works. One of the problems of traditional megasonic systems is the lack of uniformity of the cavitation field across the wafer. This causes "hot spots" — areas that see more megasonic energy (nodes) than others (antinodes) — giving rise to alternating cleaned/uncleaned areas and damaged/undamaged polysilicon lines, respectively. When more power is applied to the megasonic system to improve cleaning in lower-energy areas as a way of compensating for inadequate uniformity, there is an increase in the amount of damage to the wafer in the areas exposed to high energy. Increasing the frequency of the megasonics will not solve the underlying cleaning issues either. Only by understanding how cavitation transfers energy to the system and the nature of the sonochemical reactions that take place as a result, will it be possible to use megasonics effectively in the future.

With PRE expected to be >90% for the 45 nm node, there needs to be constant control at all stages of FEOL device preparation. When the tight incoming defectivity count allowance is coupled with the tight substrate-loss constraints, there is little room for defectivity excursions that might require added cleans. Thus, all potential root-cause sources of defects need to be carefully addressed to maintain this control in the FEOL. One typically less-scrutinized area is the wafer backside. For example, after thermal treatment from cleans, furnaces, rapid thermal anneals or oxidations, surface cracks that exist on the backside or bevel can be degraded further, and can swell and produce particles that can then be transferred to the wafer front side at subsequent processing in batch-type operations. This problem has largely been ignored because of the associated backside metrology issues and the difficulty in correlating those defectivity signals with yield-loss Pareto charts. A selective backside surface etch is required to address this defect source. This process is difficult for bench systems because of tight constraints on materials loss on the front side of the wafer and the lack of frontside/backside isolation. It opens up some opportunity for single-wafer tools, which are better suited to address this problem.

A host of novel cleaning issues will arise at 45 nm with the introduction of new gate dielectric and electrode materials. The so-called high-k dielectrics are likely to be introduced, in earnest, at the 45 nm node. These new materials will contain a host of new species that will give rise to selective etching, cleaning and contamination concerns. The most likely candidates: metal oxides, metal silicates and metal silicate nitrides, each of which will bring different challenges based on their makeup and degree of crystallinity.

New metal gate materials will be introduced in conjunction with high-k gate dielectrics. Some of the likely candidates, such as ruthenium or molybdenum, are likely to pose major challenges for wet processing, particularly in relation to the decontamination of the wafer backside. An unfortunate byproduct of the chemical vapor or atomic layer deposition used to deposit these materials is the deposition of films on the wafer backside. A wet etch will be necessary to remove the films from the backside of the wafer and prevent front-side contamination issues; many will be very difficult to remove effectively.

There may also be changes in the nature of the metal silicides used. Nickel silicide (NiSi) will be the primary choice at 65 nm and, likely, 45 nm. Metal silicides are formed by depositing the metal onto the surface of the wafer and annealing to form the silicide on the exposed silicon surfaces on the gate stack and source/drain regions. Where silicon is not exposed, there is need for selective removal of the unreacted metal. Nickel will provide some challenge for selective frontside etch and backside decontamination. There is also interest in Ni(Pt)Si, mostly at 45 nm and below, as a replacement silicide because of its ability to improve the salicidation process. The addition of even 5% platinum may introduce a challenge to remove the unreacted metal after the salicidation process. Platinum metal is difficult to wet etch, and effort to identify appropriate solutions is ongoing.