New Trends Drive ATE Open Architecture

In the nanometer era, new semiconductor manufacturing processes, such as copper interconnects, high-k gate dielectrics and low-k passivation, have become necessary. These processes, in tandem with optical proximity correction in nanoscale geometries, are creating an increasing number of new failure modes. In the past, the major failure modes were shorts and opens during the manufacturing process, or wear-and-tear failures; the pass/fail results were easy to judge according to simple logic 1/0 criteria. New failure modes, however, cause variations in delay, crosstalk among signals, spurious transients, and many other faults that are sometimes hard to define. Such failure modes require engineering judgment criteria to reflect the variables in the manufacturing process, as well as an awareness of how the device operates.

Additionally, when employing system-on-a-chip (SoC) technologies, a wide range of circuit elements require testing, such as analog circuits, high-speed interfaces and RF circuits, embedded memories and mixed-signal circuits. Thus, the large variety of tests required increases the overall cost of an SoC test.

Advantest has proposed an open-architecture automated test equipment (ATE) platform as a cost-effective means of solving test challenges that cannot be addressed by simply extending previously existing solutions.

Traditionally, at-speed functional test and AC scan using design-for-test (DFT) have been available as methods for detecting delay faults. Because increasing circuit size and complexity have led to diminished efficiency of fault detection, the effectiveness of at-speed functional test has declined, while AC scan has been subjected to intense scrutiny.

Attempting to achieve a defect rate of 100 or fewer parts per million requires reliable failure detection under multiple fault models and multiple sets of test conditions. The paradox is that, while too strict test conditions can disqualify a perfectly good part (resulting in unnecessary yield loss), relaxed test conditions can allow escapes, resulting in reduced quality of the product.

To address this dilemma, design-for-manufacturing (DFM) has been used as a mechanism to minimize failures caused by manufacturing defects and process variations. In other words, the goal is to improve yields with some design features. Widespread practice of DFM will expose the test process to dramatic change. For example, it will become normal to determine test conditions based on information from the fabrication process, making it impossible to obtain sufficient information through the test process alone.

For instance, when crosstalk noise from neighboring wires causes either signal delay or spurious transition, this test entails the complex intertwining of many elements. Improved automatic test-pattern generation is required to generate test vectors for interference caused by crosstalk. Simulation incorporating layout information is also necessary to determine which wires are prone to cause crosstalk, since the distance between interfering wires can be increased in the DFM flow to minimize failures. There is a relationship between these design tasks and test (Figure ). For nanodevices, test, design and manufacturing processes must be tightly bound together.

However, the current test environment presents problems. ATE vendors provide hardware and software built to their own unique specifications. Thus, even if one attempts to work with electronic design automation (EDA) vendors to facilitate DFT, development is exceptionally difficult without the deployment of multiple interfaces. Also, the major integrated device manufacturers have combinations of five or six types of testers in their factories, making the previously mentioned integration of processes practically impossible.

These considerations led Advantest to propose the Open Semiconductor Test Architecture (OPENSTAR) as a standard specification. Development and promotion of the standard is the task of the Semiconductor Test Consortium (STC), which was established in March 2003. It is composed of close to 50 members, including vendors of ATE, probers, handlers, test modules and parts, as well as semiconductor manufacturers and university researchers. The STC approved Revision 1.0 of the specification in May 2004, and the first OPENSTAR-compliant test platform, the T2000, is now in operation.

The current OPENSTAR standard is only a basic element for ATE. It must grow if a common test-related environment is to flourish. As it evolves into an increasingly robust environment, the STC hopes to work cooperatively for integration throughout all processes.

Nearly all the functionality of DVD recorders, digital televisions and other functions in various consumer electronic products is integrated into SoC devices. In the past, these functions were implemented by individual ICs, and their design and test procedures were developed by specialized engineers. For individual ICs, relatively inexpensive, dedicated machines could be used as test systems. With SoCs, however, multiple circuit functionalities are integrated into a single chip, causing a cost differential from the simple sum of the value of individual chips. Thus, SoC test costs are also not derived from a simple sum. Often, a test-cost reduction of 1/n is demanded, when n functions are integrated in an SoC.

This highlights the challenge faced by the test industry. On the digital side, DFT research is progressing, and high-quality test using inexpensive ATE is becoming possible. Yet DFT, in the context of analog circuit test, has not made much progress. There are two main options for reducing analog circuit test cost. First, the creation of a fault model followed by development of discrete test methods capable of efficiently detecting such faults. Or second, to follow the thinking behind DFT in digital test, minimizing the number of test points while applying a standard signal and analog scan measurement.

For purposes of surmounting this challenge, the first option is identified as a pre-competitive theme. The STC's position is that semiconductor manufacturers and test system vendors must either entrust this approach to universities as an area of basic research, or work cooperatively toward a solution. Either way, it cannot be employed in a condition in which a paucity of highly skilled analog engineers exists. However, because the fault model-based approach ignores the impact of intercircuit interference and power supply fluctuations, it cannot produce adequate quality test using present methods. Accordingly, in the case of analog circuits, it is often necessary to rely on functional test.

Testing alone cannot improve yield. Moreover, as mentioned, it is crucial to make an effort to cooperate at the level of basic research. In such an environment, it is necessary that people working in different fields exchange information efficiently. To this end, while traditional test environments were closed environments in which only a single company could operate, future test growth requires the establishment of an open, standardized test environment. OPENSTAR is an important step in that direction.