SI CHINA     SI JAPAN
Login  |  Register          Free Newsletter Subscription
Subscribe
Email
Print
Reprint
Learn RSS

Debate Over Shallow Junctions—How Low Can You Go?

-- Semiconductor International, 2/1/2001

Recent research and development in the area of shallow junction ion implantation and RTP "spike" annealing has led to recommendations on ways of continued scaling of ultra-shallow junctions to the 0.10 µm generation and perhaps beyond. Nobody in the industry argues a requirement for ultra-low energy implants to reduce junction depths by reducing transient enhanced diffusion. But the lowest practical implant energy, influenced by such issues as dopant self-sputtering and tool throughput, has yet to be determined.

With the lowering of ion implantation energy, at some point the engineer must face a trade-off between forming shallower junctions and the higher junction resistivity that results. In fact, a comparison of sheet resistance and junction depth data from many different sources showed there is more than one way to arrive at the same junction properties. Though energies can be lowered to produce junctions as thin as 30-40 nm with existing implanters, the device manufacturer must determine whether the corresponding resistivity of 400-1000 W/sq provides acceptable performance.

Aside from performance issues, a lowering of ion implantation energy leads to an increasing penalty in throughput. New studies indicate that it may be preferable to reduce the implant dose at a sufficiently low energy, according to Aditya Agarwal of Axcelis Technologies (Beverly, Mass.). Indeed, Axcelis engineers found that equivalent boron implantation results could be achieved with a lower-dose 0.5 keV implant as with a higher-dose 0.2 keV implant. This approach lessens the painful throughput penalty associated with ultra-low energy implants, which can increase process time by >3×.

In a similar manner, the spike anneal — dubbed this because of its infinitesimally short time at peak temperature — dictates a high target temperature for sufficient dopant activation and damage removal. But the peak temperature and time near peak temperature must be minimized to reduce diffusion and render an abrupt junction.


The entire implantation dose is detected in the wafer at 2 keV, but at 0.5 and 0.2 keV the retained dose is reduced by ~10% and ~20%, respectively, for a nominal dose of 1×10 15 cm -2 . For doses < 1 × 10 14 cm -2 , the decrease in retained dose due to sputtering is insignificant. (Source: Axcelis)

Spike anneals, new to the manufacturing environment, require an optimized ramp-up and ramp-down. Because the final junction profile is dominated by diffusion during the dopant activation anneal, ramp-up rate and time at temperature must be optimized to yield the best junction. Depending on the RTP equipment and process, a ramp-up rate that is too fast can lead to across-the-wafer thermal nonuniformities and poor temperature repeatability. Contrary to previous assertions, it is the contribution of the inevitable soak at peak temperature and not the ramp-up portion of the anneal that dominates the thermal budget. These were some of the findings presented by Agarwal at the latest Electrochemical Society Meeting in Toronto, Ontario, Canada.

Though commercial ion implanters have been designed to implant at energies as low as 0.1 keV, for several reasons Agarwal argues against reducing ion implantation energy too much. For one, self-sputtering — the sputtering of target material during ion implantation — can become more of an issue at lower implant energies because more atoms are sputtered off the target per incoming ion. In addition, as an increasingly significant number of dopant atoms come to rest near the surface, even more dopant is lost. Self-sputtering can lead to a 20% dose loss at 0.2 keV (Figure). Agarwal added that self-sputtering becomes even more of an issue for BF2 implants. As a result, 0.5 keV may be the lowest practical limit of implant energy.

— Laura Peters
Email
Print
Reprint
Learn RSS

Talkback

We would love your feedback!

Post a comment

» VIEW ALL TALKBACK THREADS

Related Content

Related Content

 

By This Author

There are no other articles written by this author.

SPONSORED LINKS



 
Advertisement
SPONSORED LINKS

More Content

  • Blogs
  • Podcasts
  • Videos

Blogs

Videos

Advertisements





NEWSLETTERS
Plug in and get the latest SI news, trends and industry updates delivered free, directly to your inbox!

SI NewsBreak and Special Reports (Weekdays)
Wafer Processing Report (Monthly)
Lithography Report (Monthly)
Metrology Report (Monthly)
Clean Processing Report (Monthly)
Packaging Report (Twice Monthly)
©2008 Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.
Use of this Web site is subject to its Terms of Use | Privacy Policy
Please visit these other Reed Business sites