Etch Confronts New Material Demands
Alexander E. Braun, Senior Editor -- Semiconductor International, 2/1/2001
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At a Glance | | |
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"Since 300 mm didn't arrive as early as originally expected," said Dave Hemker, vice president of new product development at Lam Research Corp. (Fremont, Calif.), "product maturity has had an opportunity to catch up, and 300 mm ramp-ups will be much faster than they would be otherwise."
Gerald Yin, vice president and general manager of Applied Materials' Etch Products Business Group (Santa Clara, Calif.), believes etch technology faces two challenges. "One is wafer performance as we move to 0.13 to 0.10 µm technology nodes, with critical issues in dielectric, silicon and metal etch. The second is productivity volume. Manufacturers want equipment that runs with consistent and repeatable performance, robust processes, low particles, and is predictable and reliable."
"Aluminum etch is still here because manufacturers like it for wire bonding," said Jason Ghormley, process support manager for Hitachi America (Carrollton, Texas). "Copper bonding will be optimized and in two years aluminum will disappear in advanced applications. Everything will go dual-damascene and most etch will be oxide etch. We'll still have STI etch, because there are occasions when the profile, such as top rounding, must be optimized to get conformal fill."
"Manufacturers shouldn't rely on bulk properties such as bulk ash rates, etch rates or selectivities to characterize capabilities," said Allan Wiesnoski, technology development manager of the Strip Product Group at Mattson Technology (Fremont, Calif.). "Trade-offs are unavoidable between what's achievable based upon bulk properties and what an optimized process can actually produce. Judging capability from a bird's eye view, without learning the trade-offs and true capabilities, application by application, will provide a poor basis for decisions."
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"The industry is transitioning to 0.13 and 0.10 µm," said Applied's Yin. "Many are already working on 0.10 µm." Yin added that applications for these architectures demand unprecedented CD control. "Current CD control is in the 10 to 20 nm range, with tools running 24/7." This precision level is insufficient for 0.13 or 0.10 µm, with wafer-to-wafer and within-wafer CD variation in a production environment having to be guaranteed to within a 10 nm tolerance. "Best case, we can control tolerances to within 5 nm, about 3 s," Yin said. "Manufacturers now expect a 5 nm CD variation at 3 mm from the wafer's edge in full-scale production. In three years, this'll be 3 nm, <2 mm from wafer's edge."
Dielectric etch faces two hurdles. One is at the front end: high aspect ratios — 10:1 and even 15:1 — and contacts with smaller CDs down to 0.13 µm for DRAMs and embedded structures. Some 0.11 µm etch contacts are already being done. "This isn't a matter of dealing with one contact depth," Yin said. "There are shallow contacts with a 3000 to 4000 Å depth, and others 0.25 to 3.0 µm deep. While we can do this now, the question is guaranteeing in a production environment a reliable contact etch with a high aspect ratio, without etch stop, and good contact resistance."
The second hurdle is at the back end: dual-damascene. Though not as challenging as high-aspect ratio contacts, the predicament lies in integrating up to seven interconnect layers to provide consistently high device yield. This would include etch, CVD deposition and resist patterning, as well as seed layers, copper deposition and CMP.
How low-k material is deposited and the dual-damascene process flow designed presents hurdles for etch. "When we have a low-k, CVD film, with fluorocarbon or hydrocarbon in it," Yin explained, "it behaves like photoresist and the selectivity between photoresist to low-k is low. Selectivity for the nitride substrate or carbon material is also low, because if you're etching through the low-k with carbon or hydrogen content compounds, you can't use a highly selective polymer-rich process; otherwise you get an etch stop." This is different when spin-on polymer material is etched since — because of different selectivities — a hard mask is needed and integration issues regarding film stability and mechanical strength arise when six or more layers are laid.
Manufacturers struggling with low-k solutions are not jumping to dual-damascene as quickly as anticipated. Those who have moved to 300 mm have started mostly with aluminum etch rather than dual-damascene. Metal etch should continue down to 0.13 µm, perhaps beyond, with DRAM manufacturers using it for several years to come.
For silicon etch, poly gates will shrink to <0.10 µm with CD requirements at <3 nm and 2 mm from wafer's edge. Yin expects this to be a great challenge for 300 mm. "Gate oxides will become so thin that high-k dielectric materials will have to be used, and gate structures will use metals like tungsten or composites. Work will continue on high aspect ratio and self-aligned contacts in the front end, and dual-damascene in the back end."
New materials, better processes
Non-volatile materials challenge metal etch. Today there is platinum etch for SRAMs and other applications. Defining smaller CDs, photomasks will become critical, requiring exotic metal etch such as chrome and quartz. The difficulty will be to ensure that not only is there a plasma source and etch chamber delivering excellent single-wafer performance, but that this is repeatable, stable and predictable.
"Fortunately, technologies that confine plasmas, preventing chemistries from interacting with the chamber walls exist," Hemker said. "Because plasma chemistries are complex, it's often more expedient to develop technologies that eliminate the potential for undesirable wall reactions and focus on understanding reactions at the wafer surface."
For dual-damascene, there is a fundamental complication with stop structures, where a trench is etched and a stop made in the middle — without etch stop layers — while ensuring that the via hole is still capped. The etch stop must be uniform across the wafer, regardless of density. This will require breakthroughs in reactors, chemistries and processes. Ion input, rf power, pressure, gas flows, and chamber wall and cathode temperatures can be controlled, but little is known about what happens on the chamber walls or what the chemical reactions are.
With six- or seven-layer interconnects, defect reduction is a major challenge. Once, most fabs tolerated a 30-particle defect density level. Lately, there is a demand to reduce this to five and there is even talk about zero defects. Defects result from the plasma chemistry and deposition, and the chamber's materials — aluminum, ceramics, quartz, polymers, carbon, silicon and others. Plasma erodes these, shedding particles on the wafer. Ensuring that chamber materials have high purity, good control and fewer particles would be a substantial achievement. Current materials are inadequate and work is proceeding to develop others better suited to plasma etch applications.
Designing for uncertainty
Lam's platform strategy focuses on inductively coupled plasma sources for conductor-type applications. "We don't anticipate CD or 300 mm limitations," Hemker said, adding that handling new materials is more complicated because not every potential combination of materials device manufacturers may consider has yet been identified. "We've addressed this through design and modeling and produced a modular, common chamber architecture. This saves time in the incremental improvement of existing — or the introduction of new — technology because components can be seamlessly introduced. If a non-volatile material is ultimately required, higher-temperature processing will be needed in etch, and it's straightforward to swap current components for heated ones." Hemker added that they have retained the reliability of basic building blocks, such as vacuum systems, pressure gauges, software, etc.
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Wet and dry processes
Mattson's Wiesnoski sees an increasing degree of integration of up- and downstream processes. "Plasma strip has evolved to include processes done on tools that normally would be just plain clean platforms — in some cases eliminating wet processing on many layers," he said.
Klaus Wolke, director of process development, wet division, at Mattson (formerly STEAG, Pliezhausen, Germany), believes wet etch will be used for nitride and oxide etch, and everything in between, such as oxynitride. "These are the only two layers suited to wet etch because this etch is typically isotropic. There still are applications involving just about every cleaning process. There's an oxide etch to remove native oxide, and over the last two years the thickness of overetch margins of oxides on silicon has dropped drastically, which means that whenever oxide is etched care must be exercised to avoid overetching."
Simultaneously, etching tolerances have increased. "We're etching from 15 to 25 Å to a 3 to 5% uniformity," Wolke said. "This is wet etching's most difficult part. Because it's slow, nitride etch isn't as critical. The crucial part is thin oxide etches requiring high uniformity. This'll become vital, since we're faced with specs that can only be measured with an AFM system. If you must etch 15 Å with 3% accuracy, you're looking at 0.5 Å accuracy — difficult to measure using standard ellipsometry."
In situ rinsing after etching — with reduced chemical concentrations — will become standard. If only 15 or 20 Å need etching, concentrated chemistries are unsuitable — dilute chemistries become necessary. The more dilute the chemistry, the better the uniformity. "We're seeing a trend toward single use of HF and in situ ending — at etch's end we dilute the HF with large quantities of DI water; otherwise uncontrolled etch can occur during the transfer from one bath to the next. Everything's done in the same tank," Wolke said. To comply with uniformity requirements, bath control must be stricter. Temperature control is less than 1°C, 0.2°C in HF-based chemistries, but accurate mixing is required, and from an equipment perspective this will be difficult.
Coping with high-k
Etch may not completely define device performance, but difficulties in performing each etching step may. "Etching orbits around materials coming into play for various device types," said Steve DeOrnellas, vice president of technology and corporate business development at Tegal (Petaluma, Calif.), "such as low-k dielectrics in integrating copper interconnects through the dual-damascene approach, where the biggest concern is in handling low-k dielectrics to etch them without disrupting the dielectric constant."
SEMATECH International has focused on high-k dielectrics in two areas: gate oxide high-k dielectric (the dielectric between the device's actual gate and the source drain area to produce a MOSFET function); and the thinning down of oxide to where SiO2 is no longer adequate because it becomes susceptible to pinholes and other problems. Nitrides and tantalum pentoxide are being investigated, as well as other oxides requiring new deposition technologies and the associated compatibility issues with those materials. When the contact etch is done, it no longer has a clean interface from the oxide to single-crystal silicon, but has the new material inserted at the contact's base that may present issues, from a selectivity and a contact resistance standpoint, depending upon how difficult it is to etch.
"We've worked on high-k dielectric materials associated with capacitor formation," DeOrnellas said. "High-k dielectrics require different materials in the device structure because they tend to transfer oxygen and are susceptible to phase changes." During etch, temperature as well as materials deposited on the features' sidewalls must be controlled because they tend to incorporate refractory metals or other materials that are difficult to remove. Throughout the etching process the wafer surfaces must be kept scrupulously clean.
Some materials are more susceptible to problems during post-etch treatments than others. High-k dielectrics are problematic not only because of the new materials in the dielectric and its etching, but because of the associated electrode materials' compatibility with high-k materials. A cascade effect occurs when new materials are introduced. There are very complex deposition, etch and lithography integration issues that need to be resolved. Considerable empirical work is required to optimize the material's physical and electrical properties to realize their benefits.
"Single-crystal silicon etching for shallow trench is becoming common," DeOrnellas said. "As we move into low-k dual-damascene, metal etch loses importance for memory manufacturers. In some larger logic devices there'll be pressure on the metal level interconnect area, where people still want to dry etch the metal, and there may even be some dry etching of copper."
As new materials come on line, they will inevitably go on 300 mm wafers, further complicating matters. Particularly in etch, because of device sensitivity (junctions are getting shallower), there will be more sensitivity to damage and particle formation within reactors. The migration to 300 mm results in 2.5× more devices passing through a single-wafer tool. More devices equals more material removed during etch, all with a tendency to deposit on reactor surfaces, pumping areas, or the wafer surface itself, causing particle and maintenance problems that limit system productivity.
Platform flexibility
Three main areas are particularly demanding, according to Dave Thomas, etch product marketing manager at Trikon Technologies Inc. (Santa Clara, Calif.). "The first is getting to increasingly smaller feature sizes and higher aspect ratios through oxide materials. The problem is that conventional oxide etch platforms tend to be medium-density plasma systems. As we go below 0.10 µm, it'll be necessary to use high-density plasma for added profile control and to maintain consistent etching, particularly with higher aspect ratios."
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The etcher is run in a high-density plasma mode for small features, fast etching, or when there is a requirement for the profile to be extremely straight. It can switch to medium-density plasma if necessary, and the process is tuned to suit the material etched as it goes through multilayers. "We used wafers with defined 0.10 µm features through a low-k material, and etched 7:1 aspect ratio features through it, showing it's possible to maintain the profile even after the strip process that removes the resist and polymer," Thomas said.
The final area is indium phosphide etching, which is becoming production-oriented. "We etch it using a hot electrostatic chuck," Thomas said. "Indium is difficult to etch quickly because it's non-volatile, while phosphorus is the opposite. Higher temperatures are necessary to make indium products more volatile, about 180°C."
Hard masks play a dominant role in etching, and oxide hard mask opens followed directly by polysilicon gate etching are becoming more common. This will be challenging because of the fluorocarbon-type chemistries required to open hard masks. If it is done in one chamber, process residues can affect selectivity when the polysilicon is etched to the gate oxide. Cluster tools traditionally used for throughput will be used for more sequential processing — the hard mask will be opened in one chamber and etch the polysilicon in another.
Thomas views equipment flexibility as vital. "We've opened hard masks and etched polysilicon in the same chamber, and been able to define <0.10 µm features — the hardware is the same. Should we go to a cluster tool, we know that the chambers for the oxide mask open and the poly are identical. As sequential processes become prevalent, vendors must produce etch chambers that are generic in design. Why must an oxide etcher have a silicon electrode? Why can't you just change the process gas to vary the process? Why must a poly etcher look completely different from an oxide etcher? There are good reasons for this, but also bad ones — large vendors tend to departmentalize their activities, ending with very different looking products."
| Etch and Strip Processes' Impact on Copper
Dual-Damascene Integration Gary W. Ray, Novellus Systems Inc. Steve Lassig, Lam Research Corp. | |
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Figure). Profile control
is necessary to meet the technology's CD and electrical specifications.
However, tapering damascene trenches and vias by a few degrees enhances
metal step coverage and has been shown to positively impact Cu defect
stress migration. The profiles produced at the features' bottom by an etch
process are less important if there is adequate selectivity to the
underlying layer. However, most manufacturers choose to eliminate trench
etch stop layers, making bottom profile control more important. Trench
etch process non-uniformity must be minimized if etch stops are not used,
to maintain adequate line resistivity control. Metallic diffusion barrier
step coverage is compromised by irregular trench bottoms or microtrenches
in its lower corners. Hard mask edge erosion must also be minimized when
etching organic low-k materials. So-called "veils" or striations often
produced on via walls by high-selectivity dielectric etches must be
avoided. Once again, metallic diffusion barrier step coverage can be
compromised if the dielectric surface is too irregular.
Via etches must be adequately selective to dielectric diffusion barriers covering the lower metal level; otherwise, copper is exposed and sputtered during the overetch step, potentially compromising circuit reliability. Values of 20:1 or greater are desirable to compensate for spatial variations in dielectric thickness and dielectric etch rate. Adequate selectivity to trench etch stop layers is also necessary, as mentioned before. In addition, erosion of the edges of vias at trench bottoms must be avoided to maintain adequate profile control. Etching trenches in via-first schemes is especially challenging when spin-on organic BARC material is used. It fills the vias to a wide range of levels depending on pattern density and via diameter. The BARC material partially shadows the trench etch wherever its height in the vias is above the nominal level of the trench bottoms. A thin ring of residual oxide is left around the vias after resist strip. The rings, or veils, disrupt metallic barrier and copper deposition resulting in poor yield or poor reliability. BARC thickness must be carefully managed. Etch processes used to open dielectric barriers over the lower metal level must be able to etch the barrier with a minimum of copper sputtering. Ideally, the process would be selective to the interlevel dielectric material, to minimize profile changes in the trenches and vias. A well controlled etch with good endpointing is also necessary to avoid excessive dielectric barrier overetch, especially if the vias are unlanded. Finally, processes used to remove photoresist and polymer residue must reduce these materials to a level that will not impact the step coverage, adhesion, or materials properties of the metals deposited later. The strip processes must not cause unacceptable changes in the properties of the dielectric materials surrounding the trenches and vias. For newer low-k dielectric films, oxygen plasmas are to be avoided as are hydroxyl amines. Dry-wet processes are in the widest use today, although considerable effort is being expended to develop all dry processes. | |
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