SEMICON West Executive Outlook

David Campbell
Vice President
Knights Technology

Design-for-manufacturing (DFM) has become a common buzzword that is sure to be a major theme at SEMICON West this year. It is getting so much attention that it is in danger of losing meaning. I have heard several different perspectives on what DFM really means and how and when it will be implemented.

At its core, DFM is about extending the process control and feedback mechanisms that have long been in place in the fab to include the design phase of semiconductor manufacturing as well. Even this is not new. Microelectronic devices have always been designed for manufacturing. The microelectronics revolution was not brought about by a new type of device, the transistor; it was brought about by a new way of manufacturing the devices. From the beginning, we have always had to consider the manufacturing process when designing new devices.

What is new is that we have pushed the semiconductor manufacturing process to the very limits of its capability and, therefore, it has become far more complex. We are dealing with larger wafers, smaller devices, new materials, new processes, and narrowing process windows — all at the same time. Variables that might not have been a factor a few years ago are now critical to maintaining manufacturing yields. Equipment and metrology vendors have responded by providing vast amounts of performance data. The challenge confronting manufacturers is extracting actionable information from that data.

As designers have pushed their designs to the limits of process capability, their need for intimate knowledge of process performance has become essential. This is the need that DFM, in its many incarnations, ultimately seeks to fill.

R.H. Havemann
Vice President of Technology, Integration and Applications
Novellus Systems Inc.

While semiconductor devices continue to scale down in terms of critical geometries and drive new process technology needs, a market shift toward expanding lower-cost consumer applications is at the same time forcing IC manufacturers to improve overall productivity and do more with less. There are two ways to address this conundrum — technology extension and productivity enhancement — and this year's SEMICON West show will likely highlight products that typify both approaches.

In meeting new technology requirements, the customer's first preference is to extend tools/processes through retrofitable "enhancements" to existing equipment, permitting tools to be used over multiple technology nodes. For example, in FEOL applications, customers are looking for ways to extend high-density plasma CVD for shallow trench isolation and premetal dielectric gapfill to the 65 nm technology node and beyond. In the BEOL, a similar effort is underway to extend physical vapor deposition (PVD) technology for copper barrier seed, which when combined with enhancements in plating tools and chemistries, enables copper fill of dual-damascene structures at the 45 nm node. So extendibility of current tool sets for dielectric and metal deposition will be a major theme at this year's show.

However, although extending current technology solutions maintains a customer's current cost structure, to be competitive, chipmakers must lower their overall costs. Common methods of reducing overall costs include streamlining process flows, improving equipment throughput, lowering the cost of consumables and increasing device yield. Equipment suppliers are the enablers of improvements in all four areas, but perhaps the greatest leverage in productivity improvement can be obtained by eliminating process steps, especially when the lower cost also gives a device performance improvement.

An excellent example of this new "streamlined technology" approach is tungsten contact fill, where an atomic layer deposition WN layer replaces the traditional Ti/TiN liner, enabling in situ contact fill in the tungsten deposition tool alone. This breakthrough process not only streamlines the process flow and lowers capital cost by eliminating the Ti/TiN liner tool, but also provides a performance improvement because of the lower contact resistance that can be achieved with a WN liner. More win-win technology solutions such as this are needed to meet the industry's difficult twofold challenge of lowering cost while simultaneously improving density and performance.

Neil Sullivan
Vice President of Technology
Soluris Inc.

With the introduction of features sizes that were smaller than half the lithography wavelength at the 90 nm process node, CD metrology requirements began a steady and irreversible transformation. Gone, for the most critical levels, is the ability to merely develop and control a process using the oversimplified, one-dimensional CD that is the distance between intensity points on a SEM image or waveform. Gone is the ability to predict circuit behavior based solely on scribe-line test structures.

Introduced was the requirement to monitor the OPC/RET-based images in their natural setting, in the two-dimensional plane of the circuit. Introduced was the requirement to monitor fully the three-dimensionality of the printed feature. Metrics such as sidewall angle, shape and footing behavior have assumed increasing importance in today's process development environment. In some cases, these metrics are being introduced in process control into the manufacturing domain.

These changes, pushed by the frenetic drive to smaller feature sizes, have opened the equivalent of a Pandora's Box for CD metrology. Scatterometry, with its promise of high-throughput, two-dimensional representation and ease of integration, has made its push into process control. The venerable CD-SEM, with its long history of steadfast support for Moore's Law, speaks loudly in its own defense. The CD-SEM has continued to fortify its dominance in process development with support of emerging OPC and RET metrology requirements and innovations like critical shape metrology for true three-dimensional feature representation, all the while quietly demonstrating process control longevity with throughput that now approaches that of the scatterometer.

It is the drama of the rapidly accelerating process changes and the effect on the CD metrology world that I inhabit that I am most curious about for this SEMICON West. To lithographers, contemplating the to-be-or-not-to-be of EUV, my world may seem like small potatoes, but I would remind them that without meaningful measurement, all is lost.

Nathan Little
Executive Vice President
Rudolph Technologies

The predominant trend at SEMICON West this year will be the continued proliferation of new materials and technologies as manufacturers seek to extend their capabilities through the 65 nm technology node and beyond. These include low- and high-k dielectrics, metal gates, advanced transistor architectures, 193 nm immersion lithography, atomic layer deposition, and more. Therefore, we expect to see an increased emphasis on inspection and thin-film metrology to develop and ramp complex new processes and maintain high yield in production.

For metrology providers, the increased demand may not translate to higher profits. The variety of new requirements will likely significantly exceed the growth of metrology budgets. Equally important, customers will demand flexible tools to accommodate their constantly changing process requirements. One solution to these problems lies in a modular design approach that provides cost-effective customized solutions for current applications with the capability to swap modules or add new ones, allowing the tool to evolve with the process.

Nick Konidaris
President and CEO
Electro-Scientific Industries Inc. (ESI)

During SEMICON West 2005, I believe the concept of cost-of-ownership (CoO) will emerge as a big focus of new product announcements from semiconductor equipment manufacturers. As we continue to migrate to the performance levels necessary for new technology nodes, customers require higher throughput capability to maintain manufacturing efficiencies. Also, while our industry matures, the need for continuous productivity gains accelerates to remain on the path of Moore's Law. At the show, I expect equipment manufacturers to introduce solutions with the technology necessary to enable customers to meet their CoO targets.

The emergence of new low-k dielectric materials and the migration to smaller nodes necessitate the transition to laser-based tools for material processing. I see the microvia-drilling, wafer-singulation and memory-trimming markets presenting great opportunities for those able to compete, as few manufacturers possess the technology to address these requirements. This trend will be evidenced by the growing number of laser-based solutions introduced at the show.

Nick Dawes
Vice President, FPD Strategic Marketing & New Business
Development, FEI Co.

Semiconductor technology has continued to evolve at a rapid pace over the past decade, despite the recent recession. Last year's SEMICON West was focused on the 90 nm node, and we are already advancing to 65 nm today, with 45 and 32 nm technology in development. With these transitions, we are seeing a major series of shifts:

• New materials are needed to enable 45 and 32 nm processes.
• New structures are needed to deliver the necessary conduction and switching speed through these smaller geometries.

This is causing major shifts in the technology supplied by the equipment industry. At SEMICON West this year, we will be seeing a trend toward equipment and solutions that address agility/flexibility and extendibility in the fab — both of which are critical to the success of semiconductor manufacturers.

Jerry Cutini
President and CEO
Aviza Technology Inc.

At this year's SEMICON West, the key industry topics will center on the drive to continue to deliver next-generation electronic devices and applications. Nanotechnology will be at the forefront of discussions as we push the envelope to get to ever smaller, faster, cheaper and more complex ICs that enable the full digital experience. IC manufacturers will look to maximizing their resources to deliver these cost-effective chips.

To this end, we'll continue to hear about accelerated development of "imperative" technologies, such as immersion lithography, the development of new precursor materials and enhanced surface films, as well as advanced deposition technologies — specifically atomic layer deposition (ALD). ALD is a market that is gaining traction on its course to becoming the "de facto" standard deposition technology. It is expected that primary ALD applications for FEOL will be gate oxides and nitrides.

We will also hear more about the growing demand for used/refurbished equipment and the rise of more sophisticated business models to support this trend. The reuse of previously used equipment is providing select chipmakers with a cost-effective choice for their production needs in order to satisfy their performance goals and budget requirements. More OEMs will promote their turnkey solutions that involve equipment selection through a formalized refurbishment program combined with installation and warranty — offering a comprehensive package so that chipmakers better manage their resources while minimizing the risk normally associated with purchasing refurbished equipment on the traditional open market.

On the business front, we will notice more repeated discussion on industry consolidation and methods of financing these consolidations and other forms of growth initiatives. Leveraged buyouts, where one acquires assets, avoid the need to start a company from ground zero because the technology and infrastructure are already in place. You can hit the ground running and focus the business on the core technologies resulting from the transaction.

These and other such trends will yield significant dialogue and no doubt be among those that gain the attention of attendees at this year's SEMICON West.

R. Keith Lee
President and CEO
Advantest America

The new trends in semiconductor devices are being driven by the strong growth of consumer electronics products. Now the largest semiconductor application, consumer products include cell phones, digital cameras, portable music players, flat-screen TVs, GPS systems, DVD players and recorders, and gaming devices. Consumers buy the most advanced products that are first to market at a competitive price. Consumer demand drives semiconductor manufacturers to accelerate time to market and continually lower costs to remain competitive.

Consumers also want mobile electronics with multiple features. The latest cell phones integrate digital video, games, e-mail, calendar, task scheduler, web access, music player and a telephone into the same portable product. The convergence of multiple consumer applications into a single consumer product increases semiconductor complexity. Advanced system-on-chip (SoC) multi-die packaging, higher-speed interfaces, higher-density and higher-speed memory, wireless, and multi-core processors are the result.

Consumers also demand high-quality products they can trust to always work reliably. Against this backdrop, to remain competitive, semiconductor manufacturers must consistently deliver reliable, advanced semiconductor devices to the consumer market, under increasingly tighter time constraints and at continually lower costs.

Bill Gately
General Manager
Philips AMS

The semiconductor industry has structurally changed over the past five years — having only a few very large capital equipment suppliers and many smaller competitors. With a handful of customers making up 75% of the capital spending, it is imperative that smaller equipment providers maintain a competitive edge. The only way to do this is to develop partnerships and innovative technologies that integrate with customers' roadmaps.

Over the next few years, it will be essential for smaller organizations to examine more joint ventures and cross-licensing opportunities in order for suppliers to maintain an acceptable level of development risk. Similar to the aircraft industry, fewer capital equipment suppliers can afford to solely undertake major development programs for an IDM's unique requirements and risk a rapid cyclical shift, which nullifies or significantly delays the need for the product. For the industry to succeed, suppliers and IDMs need to go beyond the sales relationship to develop truly mutual partnerships that are beneficial to all.

Capital equipment suppliers will need to be strategically focused to remain competitive in this new market. Many will shift to competing in profitable niches rather than attempting to gain a small share of a larger market segment defended by one of the major players. This will result in more segmentation of the capital equipment market, particularly in areas such as metrology. The new emerging equipment leaders will need to provide a variety of unique and enabling technologies that will offer a strong competitive advantage to their customers and avoid head-to-head competition with the larger players. There will undoubtedly be large-scale consolidation driven by both acquisition and competitive reality.

Kurt Lackenbucher
Executive Vice President and COO
The SEZ Group

At this year's SEMICON West, a few key trends will dominate. As the semiconductor industry continues to move toward commoditization, cost-control requirements rule will cause equipment companies to intensify their focus on optimizing chipmakers' cost of ownership (CoO). In the face of emerging 65 nm and looming 45 nm device geometries, equipment suppliers must increasingly find ways to cost-effectively meet IC companies' technology needs. Moreover, new copper-deposition, lithography and cleaning technologies create processing challenges that will make migrating to 45 nm technology extremely complex. We see suppliers focusing on extending 65 nm processes as long as possible.

In addition, the increased trend toward globalization means that companies must focus on building a global infrastructure, integrating technology with support, service and worldwide training. We would expect to see increased activity along these lines. In fact, we believe the meaning of "innovation" will shift as suppliers explore, rather than brand new technologies, innovative solutions that can be leveraged globally to optimize existing technologies. Because cost constraints will prevent chipmakers from replacing leading-edge capacity every couple years, as has been the precedent for some time, equipment makers will be looking at how to address consumables and cost drivers without forcing IC makers to constantly change or upgrade equipment.

All of this creates a significant opportunity for technologies, such as single-wafer processing.

D. Scott Becker
Vice President of Marketing
FSI International

A significant portion of the surface conditioning market is up for grabs, as cleaning experts encounter challenges with simultaneous introduction of new materials, shrinking feature sizes (creating more fragile structures) and the tightening constraints on material loss.

Historically, FEOL surface cleaning has been dominated by wet benches with megasonic energy. At the 250 nm node, megasonic energy could no longer be used in several FEOL cleaning steps because it damaged gate structures. However, high cleaning efficiency was still achievable with a non-megasonic wet bench, because high material loss, up to 5 Å, was acceptable. At the 90 nm node, non-megasonic wet bench processes are much less efficient because allowable material loss has decreased to 1 Å. For example, a non-megasonic wet bench has particle removal efficiencies of >90% for material loss of 5 Å, but close to 0% for material loss of 1 Å or less.

We are in the midst of an interesting race where no one cleaning technology has proven itself to be the heir apparent for non-damaging, low-etch particle removal. Wet bench technologists are actively improving megasonic energy fields and controlling dissolved gases to eliminate hot spots, and are reducing material loss by using dilute chemicals. Centrifugal batch spray technologists have successfully demonstrated higher particle removal efficiencies compared with non-megasonic wet benches because of greater hydrodynamic forces. Single-wafer spray technologists have had success incorporating high-velocity spray jets, but have experienced limited adoption caused by high cost. Cryogenic aerosol technologists have had excellent success in high-volume manufacturing for removal of fall-on defects with a non-damaging, zero-etch process.

IC makers will continue to employ a variety of cleaning technologies to address the wide range of challenges.

John Odom
President
DuPont EKC Technology

Smaller, faster, better" has been the mantra of the semiconductor industry for some 30 years, and despite many technical obstacles, it has maintained a steady rate of geometric scaling, which has enabled dramatic improvements in cost per function.

Technology requirements become significantly more challenging in the nanoscaling integration era at BEOL, with the introduction of new materials and processes for copper and low-k dielectrics through 45 nm and beyond.

The complexity and diversity of these materials can result in cleaning challenges after etching because of the deposition of unwanted post-etch residues. Many of the newer low-k materials can readily degrade if exposed to excessive plasma processing. For damascene integration to succeed, a selective method for removing these residues without corrosion, loss of critical dimension or increased permittivity is needed.

Scaling has also introduced new technologies within wafer-level packaging, which is predicted to see major growth over the next few years. Electroplated bumping processes on leading-edge devices require new resist removers compatible with sensitive metals and other materials.

At the heart of the scaling phenomenon is the CMOS transistor structure and its implementation on silicon. In conjunction with geometric reductions, high-k dielectrics will be needed, along with the use of metal gates with specific work functions.

George Celler
Chief Scientist
Soitec

The 45 nm technology IC node will be marked by two distinct technical strategies — one focused on high performance and one driven by system-on-chip (SoC) applications, including low-power, portable-RF applications.

Those on the high-performance path will continue to be the drivers for the most advanced substrates and will be the material innovators. Ultrathin silicon on insulator (SOI), mobility-enhancing substrates like strained SOI (sSOI) in addition to local strain techniques, as well as improved thermal dissipation to reduce the impact of hot spot impact, are among the most obvious engineered substrate solutions. Device architectures are likely to remain planar with finFETs on the horizon for the 32 nm node for the most aggressive IC players.

The coupling between engineered wafers and device architecture will grow even closer. Partially depleted approaches will push the mobility- enhancing substrates, while others may switch to ultrathin, fully depleted SOI in order to improve electrostatic device characteristics. Each way presents its own set of technical advantages and challenges.

On the other hand, those pursuing advanced RF SoCs will take advantage of high-impedance SOI substrates with a high-resistivity handle wafer, while SOI with ultrathin buried oxide (<50 nm) will enable IC architectures where n and p regions are defined in the handle substrate for back-bias generation through the buried oxide. Since attaining the highest performance is not the focus here, these SOI CMOS solutions will target the lowest power consumption and longest battery lifetime. Low-standby and low- operating power devices will be built by taking full advantage of dielectric isolation, while high-resistivity substrates will substantially improve performance of passive components, such as inductors, that are placed directly on the silicon chip.

Demands of future circuits, regardless of specific application, will continue to drive the development of specialized engineered substrates.

Bret J. Bergman
President and CEO
Qcept Technologies Inc.

Next-generation lithography is always a popular topic at SEMICON West. This year, as immersion steps out as a prominent method for 65 and 45 nm lithography, discussion will finally turn to the elephant in the room — defects. Because of the increased risk of printing errors caused by bubbles in the fluid between the lens and wafer, immediate defect detection is critical. Another concern to be addressed is the possibility of precipitates on the wafer surface left by less than perfect waters.

Sematech has called out immersion lithography as a top technical challenge for 2006, noting that prototype immersion tools are already shipping to advanced fabs. While immersion is admittedly an early-stage technology, there's little question that many challenges to its adoption have already been addressed and will find a place in production. Advanced fabs already using the new tools must resolve the defect issue quickly, and in the race to be first, they will surely bring up potential solutions with suppliers at this year's conference meetings. One method up for discussion: inspecting the surface of the wafer, both before and after the immersion lithography step. This method will provide real-time feedback to prevent yield hits and also serve as an important quality monitor on the emerging field of immersion lithography.

Steve Chisolm
President
Pall Microelectronics

This year's SEMICON West will affirm that, in this industry, constant change is inevitable. One of the key areas where constant change is providing opportunity is the adoption of alternative and innovative technologies. While the semiconductor industry has traditionally adapted outside manufacturing processes for the wafer fab environment, pressure is mounting to find additional alternatives to keep making chips faster, smaller and cheaper. Inserting inkjet lithography, imprint lithography or organic devices into semiconductor manufacturing is going to require extraordinary efforts to meet the stringent purification needs of sub-45 nm chip processing.

Incorporating these technologies into semiconductor processing will require unique purification techniques to remove contaminants and separate unwanted molecules, leaving only those molecules that help improve device performance. Such purification techniques will enable users, for example, to classify organic polymers based on molecular weights, leading to better devices and material use optimization.

From a business perspective, the integration of these new technologies into leading-edge semiconductor processes will help bring new opportunities to the global chip industry.

It's likely that the meetings and discussions at this year's SEMICON West will center on finding new ways to utilize individual companies' expertise. Some companies will seek consolidation and critical mass, often through mergers of equals. This can leave customers with a limited choice of materials, equipment or components. Selecting the best-in-class in each area, through carefully screened and strategic partnerships, is vital to achieving the optimum solution.

Bernold Richerzhagen
President and CEO
Synova SA

During SEMICON West 2005, show activity will again center on optimization of manufacturing techniques for chips to be used in cell phones, handheld devices (e.g., PDAs and palmtop computers) and other consumer electronic products. This "killer market" is now the predominant driver behind a host of device and packaging requirements that semiconductor equipment makers must find innovative new ways to accommodate.

For example, chipmakers are increasingly focused on component miniaturization, which calls for devices that are lighter in weight and consume less power. New approaches to wafer thinning — a key miniaturization technique — are an important trend that both equipment and materials suppliers are addressing. In the materials arena, we are seeing the emergence of low-k dielectrics and compound semiconductors such as GaAs, which help improve chip performance. In the equipment sector, coping with these complex new materials requires an accelerated transition to laser-based solutions, particularly for wafer and package singulation. Older, saw-based technologies cannot handle these fragile materials without incurring damage, downtime and, ultimately, loss of yield.

This leads us to cost of ownership (CoO), which will likely be a major focus of announcements from equipment manufacturers. SEMICON West provides an ideal forum for companies developing new techniques to educate the industry about the benefits of their solutions for optimizing chipmakers' CoO.

Mark Namaroff
Vice President of Marketing
Axcelis Technologies

For the first time in more than 25 years, ion implant manufacturers and end users are taking a fresh look at the implant landscape, and discussions at this year's SEMICON West will move away from talk of traditional beam current applications and toward a more thorough review of application needs through the 32 nm technology node.

Traditionally, ion implantation is categorized in one of three segments: medium-current, high-current or high-energy. However, in practice, we know ion-beam currents do not drive device behavior; a device ultimately behaves according to the dopant dose. This is why manufacturers have been able to use different implanter types for common applications. In many fabs, for example, transistor channels traditionally doped using medium-current systems are built with high-energy and high-current implanters.

Today's scaling of energy ranges expands the potential for implanter segment overlap, particularly as channel dopant processes scale into the mid-dose, low-energy regime and a variety of supplemental (non-dopant) implants are employed to modify ion channeling and dopant diffusion characteristics. Many factors can affect the decisions about which platform(s) an end user chooses, including capital cost (the total number of systems required); operating cost (dependent on the number of types of systems employed); lot cycle time (dependent on the lot size distribution); and device technology roadmap (particularly, the level of process control required).

Different solutions will fit different fabs, depending on objectives, but the implant community will be looking for tool platforms that can help them manage all of their emerging implant needs with broad application coverage.

Rick Hazard
CEO
Lightwind

At this year's SEMICON West, a significant focus will be on the trend of meeting the challenge of transitioning to 45 nm and beyond. An area that will receive much attention will be new strategies in advanced process control (APC). The importance of APC to effectively control process drift in tools will increase as the linewidths and margin for error shrinks. At 45 nm, it will be a virtual requirement to monitor, in real time, the chemical compounds and activities in all stripping, etching and deposition processes to detect the smallest of variance before it drifts out of the process window — or worse, leads to a catastrophic process failure that today may only be detected at electrical test.

It is thought that more than 10% of device manufacturing failures today are a direct result of undetected chemical variances and faults during processing. Imagine the rate of failure at 45 nm processing if nothing changes. A real-time monitoring method that is non-invasive and provides immediate and accurate data is required. Chipmakers can then take immediate preventive measures.

A number of fabs are finding that the most effective way to achieve this is to monitor the process chamber against a template before each wafer is committed to the process, and measure the exhaust for composition of the chemical byproducts as the product is treated. Adding real-time chemical monitoring to APC strategies will significantly help speed the successful migration to 65 nm and provide the process monitoring required for 45 nm production. I expect real-time process monitoring, particularly chemical monitoring, will become critical to successful development and deployment of the 45 nm node.

Linda Capuano
Executive Vice President
Advanced Energy Industries Inc.

The IC manufacturers are moving to smaller lot sizes and lower production costs, as the semiconductor industry moves to larger wafer sizes and smaller dimensions. The ITRS predicts that, in the limit, a production lot may consist of a single wafer with a depreciation cost of more than $8000 per wafer in 2009. These trends mean that every process must continuously operate within ever-tightening statistical control limits. The demands on sidewall profile control, cross-wafer uniformity, and wafer-to-wafer repeatability for the plasma etch process are particularly challenging to IC manufacturers.

These challenges create opportunities for equipment suppliers who can provide etch processing tools with independent control of plasma density and ion energy, increased instrumentation and control for plasma stability and uniformity, as well as endpoint detection. To the subsystem and component suppliers, this means providing extremely stable, fast-responding, multiple-frequency power delivery systems, precise gas flow control, and advanced instrumentation subsystems. Further, there continues to be demand for component-level embedded LAN communication and control.

At SEMICON West this year, visitors will see many product offerings for, and engage in discussions about, advanced technologies that address these challenges at all supply chain levels: IC manufacturers, equipment makers and subsystem suppliers.

Phil Dembowski
Global Market Manager, Semiconductor Fabrication Materials
Dow Corning Corp.

SEMICON West 2005 will reveal that the long-standing discussions around spin-on and CVD technologies are far from over, as some may have presumed. In recent years, CVD-based low-k processes emerged as a winning approach, at least through the 65 nm technology node. This is evident in the strong growth in CVD precursors for low-k and copper barrier applications at the 90 nm node and, by extension, the 65 nm node.

Work continues throughout the industry to demonstrate CVD precursor technology for the 45 nm node, where users desire k values <2.5, yet must maintain sufficient mechanical strength. But it's too early to say spin-on is dead. At the 45 nm node, customers are still looking at both CVD and spin-on as potential solutions.

Moreover, both CVD and spin-on technologies are gaining renewed interest for a myriad of other applications. In the spin-on area, silsesquioxane-based technology continues to be incredibly strong, particularly for aluminum interconnect dielectric, gapfill and planarization applications. Expect to see manufacturers applying this spin-on technology to other applications, such as shallow trench isolation fill, premetal dielectric and sacrificial films.