Next-Generation Low-k Focus of IITC

Low-k dielectrics now in use for the 90 nm generation are typically SiCOH films, with a k value of around 3.0. To push to lower k values, many believe it will be necessary to move to porous materials. These materials have a lower k value, ranging from 2.3 to 2.9, but they also introduce a new set of integration and reliability challenges. Most notably, porous materials can easily absorb and retain moisture. The lowest k value achievable is that of air (1.0), which is why porous materials have a lower k value, and also why there is an interest in moving to air gaps as a replacement for dielectrics in advanced interconnect structures.

At the International Interconnect Technology Conference (IITC), to be held June 6-8 at the Hyatt Regency San Francisco Airport Hotel in Burlingame, new low-k dielectric technology is a major focus. Following are some highlights of the work scheduled to be presented.

Researchers from the IBM, Sony and Toshiba alliance will detail the reliability assessments they made for chips built in a standard 65 nm manufacturing process, with a SiCOH dielectric and nine levels of copper interconnect. They found that a 20% porosity SiCOH material (k=2.8) had excellent electrical and mechanical characteristics. It was also suitable for wire bonding (chip-to-package connections), a key requirement for mass production.

Meanwhile, a Freescale, Philips and STMicroelectronics team has studied 65 nm chips using either dense low-k OSG (k=2.9) or ultralow-k porous OSG (k=2.5) dielectrics on bulk silicon or SOI substrates. Their aim was to assess the materials' mechanical reliability. They studied aspects such as wire bond pad design, interconnect design rules and assembly techniques, all with an eye toward identifying the best combinations of substrate, interconnect and chip package from a mechanical reliability viewpoint. They then built test chips to verify the model predictions, and demonstrated adequate mechanical reliability for a wide range of 65 nm chip types.

In longer-term, more fundamental work, researchers from Toshiba will discuss how they reduced damage and controlled moisture in dielectrics for 45 nm technology. They used a hybrid scheme: a SiOC dielectric with a buffer for the via layer, and a damage-resistant organic dielectric for trench sidewalls (polyarylene, k=2.3). In damascene processing, the plasma used to etch trenches in the dielectric material can damage the sidewalls. The hybrid approach enabled them to greatly reduce common copper interconnect problems, such as stress migration and electromigration.

Fujitsu researchers will describe how they successfully integrated multilevel copper interconnects and porous ultralow-k dielectrics at the 45 nm node. Their ultralow-k material is nano-clustering silica (NCS, no k value given). NCS has small, well-distributed pores and a coefficient of thermal expansion quite close to copper's, meaning they expand and contract in lock-step. This reduces thermal stress, one of the main issues with ultralow-k interconnect systems. The researchers also built 70 nm vias, using 193 nm lithography. They achieved yields of >90% in a chain of 1 million vias. Further, the time-dependent breakdown of the system — a key measure of dielectric robustness — was equivalent to that of 65 nm technology.

A Selete team will describe how UV-curing technology improved the mechanical properties of a porous, plasma-enhanced CVD SiCOH ultralow-k dielectric (k<2.4). The researchers used it in a two-level copper interconnect system with 65 nm design rules. They saw dramatic improvement in the hardness of the porous film with little shrinkage, and also much lower electrical leakage. While other treatments exist to harden porous low-k films (plasma cure, chemical annealing), the advantages of UV curing are process simplicity and less chance of damage to the film. They say the technique can extend to 45 nm technology and beyond.

Because air is the perfect dielectric, much work has gone into trying to create air gaps to insulate copper lines, especially for the coming 45 nm technology node. Philips researchers will describe a promising integration scheme that combines ease of manufacturing with good mechanical stability and electrical results. They built a range of comb-like structures by decomposing a thermal-degradable polymer in the desired spaces, after formation of the IMD level (Figure ). The decomposition products out-diffused, leading to air cavities at the trench level. Effective k values as low at 1.45 were obtained for non-passivated samples, while for a simulated two-level structure, an effective k<2 was obtained, showing potential for use in the 45 nm generation of chips. Surprisingly, copper electromigration was no worse than in standard copper interconnect systems. Promising lifetimes were obtained as well.

Philips researchers built this 120 nm comb structure by decomposing a thermal-degradable polymer, leaving air cavities. Such air gaps, which provide the lowest k value possible, could come into play in advanced interconnect structures.