Damage Mechanisms in Porous Low-k Integration

The 2004 International Technology Roadmap for Semiconductors (ITRS) calls for the use of low-k dielectric materials (k_eff <2.6) at the 45 nm node.¹ The low-k dielectric market currently offers a wide variety of porous and non-porous low-k dielectric materials.² Introduction of porosity is one method to obtain low dielectric constant. Along with the introduction of porosity comes a laundry list of processing challenges. These challenges include poor mechanical strength and higher susceptibility to contamination during wet and dry processing steps, as well as the degradation of the electrical properties of the dielectric caused by damage during the integration process. Some of these challenges adversely affect intraline capacitance, as described by k_eff.³ For example, the k_eff could be lowered if the etch-stop layers are eliminated. However, elevation of k_eff because of dielectric damage would still need to be addressed. Therefore, there is an urgent need to understand the impact of process chemistries and integration schemes on dielectric damage and k_eff.

The purpose of this article is to illustrate techniques used to measure dielectric damage, identify some of the sources of low-k damage and assess their impact on the RC product.

We performed preliminary work to establish a physical method to measure dielectric damage on blanket wafers. This method was then extended to pattern wafers with structures that could be electrically tested and used for k_eff extraction. We used a spin-on porous MSQ material (k~2.2) as the low-k dielectric test vehicle. Figure 1 shows the serpentine test structure used for electrical testing.

In addition to electrical testing, we characterized dielectric damage using a specially developed staining method, X-ray photoelectron spectroscopy (XPS), and transmission electron microscopy electron energy loss spectroscopy (TEM-EELS) analyses. In some experiments, a thicker dielectric stack was used to understand the impact of etch parameters, such as etch time and power on damage.

1. Serpentine test structure that underwent electrical testing as well as a specially developed staining method, XPS and TEM-EELS analyses.

Plasma damage measurement

The choice of method is governed by cost and throughput. The simplest, quickest method for estimating damage is staining with dilute HF. Undamaged porous MSQ does not etch in this medium, whereas damaged MSQ is similar to oxide and etches readily (Fig. 2 ). The damage is quantified as the difference in widths of the hardmask (HM, a) and the minimum line CD (b). Feature (b) shows more etching than (c) caused by extended exposure to etch and ash plasmas. The ratio of the etch depth into the low-k relative to the damage (d/[a-b]) is known as the depth-to-undercut ratio.

2. Damaged low-k film (MSQ) is readily etched in dilute HF, though the top SiC hardmask is not. The depth-to-undercut ratio (d/[a-b]) can be used to compare different etch chemistries.

This ratio may be used to compare different etch chemistries. The method shows good repeatability, but can be subject to large error when measuring smaller undercuts, and may cause pattern collapse on smaller-geometry features. For this reason, the test structure developed for comparative work is a thick low-k film with a SiC hardmask. This allows longer etch times to be investigated. The feature chosen is a 0.5 µm trench, which is robust enough to allow long HF staining times and deep undercut, but will not suffer from pattern collapse. We also employed TEM-EELS analysis for carbon depletion, as well as electrical test data for integrated structures, to further examine etch damage.

The following section describes some of the sources of dielectric damage and illustrates some of the process parameters that could alter the extent of damage. Finally, we will show a correlation of dielectric damage and RC product. RC is the product of the serpentine resistance and the comb capacitance, and is proportional to k_eff.

In the reactive ion etching (RIE) process, C_xF_yH_z-based gas chemistries react with the Si-CH₃ bonds in the porous low-k to form CF_x and some silicon-containing volatile byproducts. In the subsequent O₂-based photoresist strip process, the CF_x compounds decompose into volatile species, such as CO and CO₂. As the O₂ concentration in the photoresist strip chemistry is increased, the CF_x polymer is removed more efficiently.

Carbon depletion from the surface of the low-k dielectric leaves behind several dangling silicon bonds. When these species come into contact with the moisture in the ambient, Si-OH bonds are formed. This change in composition of the dielectric material leads to an increase in dielectric constant of the material, often on the order of 0.5 or higher.

The effect of different etch chemistries on damage is shown in Figure 3 . All samples received the same hardmask open etch followed by a low-k etch for 30 or 60 seconds. The chemistries used were a non-polymerizing CF₄/O₂/Ar (hardmask etch, a and b) vs. a C₄F₈/Ar/N₂ (low-k etch) polymerizing chemistry (c and d). The depth-to-undercut ratios for (a) and (b) are 5.8:1 (30 sec) and 8.1:1 (60 sec), relative to 4.0:1 (30 sec) and 3.3:1 (60 sec) for the HM etch, showing a marked increase in the damaged area for the additional low-k etch depth.

3. The effects of different etch chemistry on depth-to-undercut ratio. All samples received the same hardmask open etch followed by a low-k etch. The C4F8/Ar/N2 results (a and b) showed a depth-to-undercut ratio of 5.8:1 (30 sec) and 8.1:1 (60 sec), respectively, vs. less damage for the non-polymerizing CF4/O2/Ar chemistry (c and d), with depth-to-undercut ratio of 4.0:1 (30 sec) and 3.3:1 (60 sec), respectively.

For the polymerizing etch chemistry, we conducted some experiments on varying single inputs to the process, with results shown in the Table .⁴

Ash damage

Adding an ash to the above etch process results in further damage. The SEMs (Fig. 4 ) show a CF₄/O₂/Ar etch process before and after an extended ash. The increase in undercut and depth is due to damage caused by the ashing chemistry on all exposed surfaces. The depth-to-undercut ratio, as a function of ash times for both the C₄F₈/Ar/N₂ and the CF₄/O₂/Ar chemistries (Fig. 4 , right), shows immediate onset of damage in the ash process for the non-polymerizing chemistry, whereas the polymerizing chemistry demonstrated a delay in the onset of damage by ~30 seconds. This result suggests the polymer is protecting the sidewalls from the ash effects in the early part of the ash process. After 30 seconds, sidewall damage in the polymerizing process occurred at approximately the same rate as with the non-polymerizing process. The non-polymerizing process does not show an increase in damage as the ash time increased after 30 seconds, suggesting the damage occurred early and is self-limiting. For a given ash plasma, it appears unable to penetrate beyond the dense film formed in the early ash stages.

4. Ashing in CF4/O2/Ar caused both increased depth and undercut (left). The polymerizing chemistry (C4F8/Ar/N2) protects the sidewall in the initial 30 seconds from damage, whereas the non-polymerizing chemistry (CF4/O2/Ar) causes immediate damage (right). In both cases, ash damage is self-limiting.

Post-etch photoresist removal has been shown to be a considerable challenge for porous low-k integration. Since most ultralow-k (ULK) films are high in carbon, ashing of photoresist can damage the ULK film by the same mechanism of volatilization of carbon species. For this reason, the traditional high-temperature, oxygen-based isotropic ash processes can no longer be used. The industry is now moving to either very directional RIE ash processes or hydrogen-based isotropic ash processes, depending on the integration scheme. Although we have seen that the dielectric damage is initiated during the etch process, it is the photoresist strip (or the ash) process that causes more severe damage. We examined electrical data for these processes.

We processed a parallel set of trenches with different ash processes, then deposited metal to measure RC. The stained SEM images (Fig. 5 ) are arrived at using a combination of chemistry and tool. The resulting RC product was compared to the undercut. The ash processes that lead to higher RC product and greater undercut corresponded to a higher k_eff value.

5. Stained images of trenches processed with different ash processes.

A single-damascene structure with porous MSQ was used for the ash process development. We used three different tools to test the ash processes:

• Capacitive etch tool: N₂/H₂ at 40°C.
• ICP standalone ash tool: N₂/H₂ at 10°C.
• ICP standalone ash tool: He/O₂ at 10°C.
• Downstream ash tool: He/H₂ at 270°C.

Both the etcher and the downstream He/H₂ ash had high inherent non-uniformity, which means the percentage of over-ash needed was higher for those tools. This downstream, isotropic process was mainly controlled by temperature. The ICP ash tool gives excellent uniformity of ~3% (1 µm).

RC was calculated from the serpentine resistance and the comb capacitance of the 0.125/0.175 µm features (Fig. 6 ). The capacitive etch N₂/H₂ ash process shows the lowest RC, followed by the ICP N₂/H₂ ash process and the downstream He/H₂ ash processes. The ICP He/O₂ ash process showed degraded RC products, which indicates low-k damage. Both N₂/H₂ ash processes were examined by TEM-EELS (Fig. 7 ) in order to investigate carbon depletion as the source of low-k damage. The carbon depletion can be seen as a decrease in the carbon EELS signal, along with an increase in the oxygen EELS signal.

6. The capacitive etch N2/H2 ash processes show the lowest RC, followed by the ICP N2/H2 ash process.

7. Carbon depletion can be seen on the TEM and also as a decrease in the carbon EELS signal and an increase in the oxygen EELS signal.

EELS analysis showed high oxygen signal at the interface between the copper barrier and into ~20 nm of the low-k interlevel dielectric (ILD). The two N₂/H₂ ash processes show ~15 nm of carbon depletion.

Since a hardmask layer protects the low-k dielectric during copper CMP, no damage is expected, as copper slurries are normally highly selective to the barrier or dielectric hardmask. However, during barrier polish, thinning of the hardmask by overpolish is usually performed.⁵ Such a process may be necessary to achieve the lowest overall k_eff of the stack, especially if a hardmask with higher dielectric constant is used. Figure 8 shows the change of capacitance caused by thinning of the hardmask by CMP. It is expected that the capacitance will continue to decrease (both due to a decrease in stack thickness and decrease of the capacitance contribution from the hardmask layer) upon continued polish through the stack. However, when the entire hardmask is polished away, the capacitance increases, indicating damage of the low-k dielectric.

8. As the hardmask is being polished, capacitance decreases until the low-k dielectric is reached, and capacitance increases due to moisture absorption.

Moisture absorption during CMP is of primary concern because of the aqueous nature of the process. Water has a very high k value, and any residual moisture will increase the stack capacitance. On annealing these wafers, there is ~13% reduction of the capacitance for wafers with the hardmask, while, for wafers without the hardmask, the capacitance can decrease by ~22%, demonstrating some recovery of the damage. However, the RC product is seen to increase by ~6.5%, compared to the wafer with a thin residual hardmask, indicating the existence of residual damage. These studies show that the damage from direct CMP is not entirely caused by moisture absorption and there is a non-recoverable component.

To investigate the chemical and structural changes caused by direct CMP, blanket ULK wafers were polished and FTIR spectra⁶ of post-CMP wafers were compared with an unpolished wafer. For both Si-CH₃ and Si-O-Si, area under the peak was calculated and normalized for thickness. The ratio of these peak areas (Fig. 9 ) indicates carbon depletion and creation of excess Si-OH groups, which both degrade the k value.

9. The ratio of Si-CH3 to Si-O-Si peaks from FTIR indicates carbon depletion or the creation of excess Si-OH groups. Both processes increase keff.

Conclusions

We studied process-induced damage on a porous low-k dielectric. HF decoration method, along with TEM-EELS, was used to physically measure damage, while RC product was used to understand the impact of damage on electrical performance of the structures. The extent of plasma damage is related to the nature and diffusivity of the plasma species. This, in turn, is related to the type of etch or ash tools used during the processing. For example, the capacitive etch N₂/H₂ ash process showed better performance compared to the ICP He/O₂ ash process for the same low-k dielectric. In the case of the etch process, sidewall polymer control is a key element in the design of low-damage etch processes. Another source of damage that needs to be minimized originates during CMP. It was seen that, with gradual thinning of the hardmask during the barrier polish step of CMP, capacitance decreases. Eventually, when the low-k dielectric is exposed, the capacitance increases due to moisture uptake. Attempts to remove the moisture showed that only a partial recovery of k value was possible.

With the current integration schemes, porous low-k dielectrics and the toolsets, the dielectric damage is about 30 nm along the sidewall. Extrapolating these observations to the 45 nm node dimensions with 65 nm low-k dielectric spaces, about half of that dimension would be affected by dielectric damage. In order to successfully integrate porous low-k materials, it is important to contain the damage within 5 nm. Rather than focusing solely on new lower-k and more porous materials, this work emphasizes the need for materials that can undergo the various processes during integration with minimal damage. In addition, integration schemes that call for less damaging processes will be essential.