Reduction Lithography: An Enabling Technology for MEMS

Microsystem technology (MST) and its offspring, microelectromechanical systems (MEMS), are rapidly going mainstream, as these functionalities are being successfully integrated with electronic functions based on CMOS process technology. MEMS devices manufactured using CMOS-compatible technology include pressure sensors¹ and RF components,^2,3 to name just a few. There are multiple drivers for this trend, ranging from increased device functionality to more compact end products to economies achieved by fitting so many MEMS devices on a single wafer.
 
In many cases, increased functionality is achieved by integration. Putting filters, antennas or accelerometers, and driver ICs or amplifiers in the same small-footprint device enables many new functions in electronic or communication equipment. Examples include vibration control in cameras and multiband cell phones. Moreover, reducing device size by combining functionalities enables smaller electronic equipment, which saves OEMs money while providing more convenience to consumers. The shrinking form factor of cell phones is an obvious example.

Adding MEMS technology to "commodity" IC wafers delivers a higher added value to each wafer, and opens the door to innovative content. In this way, semiconductor manufacturers can realize higher margins on their products; however, it is worth noting that cost reduction per functionality is not always a valid motivation for MEMS integration with CMOS, because it is important to realize that yield issues derived from manufacturing a combined stack may become a burden.

Another driver of the trend toward integrating MEMS and CMOS processes is higher utilization of existing equipment. In many cases, equipment that has been used for IC production for years is readily adaptable to run CMOS-compatible MST processes. In this way, a single tool type can produce both the MEMS device and the driver IC, which obviously leads to a relatively small tool footprint. Combined with the innovative content mentioned above, this has become an accepted business model in the semiconductor industry.

Last but not least, MST devices in general are fairly small, which means that very large quantities of devices fit on a single wafer. This is an important reason why the global wafer production of MEMS devices is small compared with mainstream IC products, and it also explains why MEMS production today is mainly on 150 mm or smaller wafers. However, integration of MEMS devices with driver ICs manufactured by CMOS technology may lead to an increased use of 200 mm wafers in MEMS manufacturing, because MEMS devices are built on top of these CMOS wafers.

All these considerations lead to the fact that many MEMS manufacturing processes are now running on or being transferred to reduction stepper technology, and it's worth noting that this brings some additional benefits to the MEMS manufacturing arena. While older reduction stepper technology always obeyed the International Technology Roadmap for Semiconductors (ITRS) rules that prescribed the required resolution and overlay performance, MEMS manufacturing has different requirements. These requirements depend on the specific device and include:

• Large depth of focus and exposure of thick resists.
• Very tight CD control relative to the structure dimensions.
• Double-sided alignment for processing both sides of the substrate.
• Large focus-to-alignment offset in case of a high-aspect-ratio topography.
• Good stitching-and-butting control to expose large area devices.
• Flexibility in material handling (small wafers, even pieces of material).

Several requirements are met with existing reduction stepper technology, while others have been specifically developed for the MEMS manufacturing industry.

A preexisting feature that meets this challenge is the excellent CD (critical dimension or linewidth) control of reduction steppers (Fig. 1 ).⁴ Applications of this CD control are in the fields of optical devices, where linewidth variations must be very small (e.g., <50 nm for 2-3 µm wide lines); and for pressure sensors, where the piezo elements' dimensions must be well-controlled (e.g., better than 0.5 µm for 30 µm structures) to achieve a large linear performance range of the sensor.

1. CD uniformity performance for several optical lithography techniques.

2. SEM photograph of 5:1 aspect ratio image of dense 1:1 lines and spaces. 10 µm thick resist i-line illumination. (Source: MicroChem/Nippon Kayaku)

Another preexisting enabler of MEMS technology on reduction steppers is the good photosensitivity of modern, thick i-line resists. Following the ITRS, the requirement of thick resists and high aspect ratios never existed, but recent developments have shown the capabilities of i-line illumination (Fig. 2 ).

Another capability that reduction steppers enable in MEMS manufacturing, as a result of the ITRS requirements, is excellent alignment. Several derivative capabilities come from this basic feature, mostly after some additional engineering and development efforts:

• Large focus-to-alignment offset in case of a high-aspect-ratio topography.
• Double-sided alignment for processing both sides of the substrate.

The large focus-to-alignment offset is enabled by the superior angle control of the alignment laser beam of some older steppers, which leads to layer-to-layer overlay control of better than 150 nm with a topography of 100 µm.⁴

A major breakthrough for MEMS manufacturers is the submicron alignment performance in the field of double-sided processing. At the same time, this technology is made available on an industrial production platform.⁵ At ASML, this alignment technology is called 3DAlign, and it is based on a set of two (or four) targets — alignment markers — that contain a grating in both the X and Y direction. By directing a laser beam through the reduction lens onto the markers and detecting the reflected laser beam signal that contains phase-grating contrast information, a very accurate alignment method is provided (Fig. 3 ). Over the past two decades, this so-called Through-The-Lens (TTL) alignment technology has proven its value in numerous semiconductor applications using front-side alignment.

3. Basic principle of double-sided alignment with 3DAlign.

At first glance, this alignment scheme looks elegant and simple: The exposure wafer table contains a pair (or two) of optical modules through which the alignment laser beam is directed to the alignment markers on the backside of the wafer. The reflected signal produces an image of the alignment marker in the focal plane of the wafer, and the alignment procedure continues as if it were standard front-side TTL alignment. But behind the scenes during an alignment cycle there is significant calibration, referencing and characterization of optical properties, which enables relative or absolute positioning. Construction of the wafer table represents hundreds of independent design parameters.

Together, these features lead to unprecedented accuracy that can be applied in a volume-manufacturing environment. The double-sided alignment capability is one of the essential processing technologies for the manufacturing of many optical and inertial MEMS devices, for back vias in the back end of compound semiconductor manufacturing, and as a supportive technology in system-in-package (SiP) devices. The overlay performance of device layers on opposite sides of the substrate is<250 nm with 3DAlign, which enables the generation of many new devices and process technologies.⁶

Small piece material handling

4. Example of small piece handling for a reduction stepper, while maintaining good overlay performance.

The capability that requires the most flexibility in MEMS manufacturing is material handling of small pieces. The use of expensive substrate materials in combination with the R&D nature of the device development (mostly low-yielding processes) makes small piece (wafer pieces) handling a requirement. Because of this, dedicated developments for existing reduction steppers have been performed, such as the 10 × 10 mm piece handling technology shown in Figure 4 , which has proven to be cost-efficient for R&D in the field of InP and superconducting substrate materials.

In summary, fully developing MEMS potential for a variety of applications ultimately will require new dedicated tools and compatible processes. But the good news for semiconductor manufacturers today is that IC process technology and existing reduction steppers enable the integration of MEMS functionality into many types of ICs, which creates economies for device manufacturers and enhanced functionality for end users.