Bernie Meyerson, Vice President and Chief Technologist, Systems & Technology Group, IBM

Bernie Meyerson (Source: IBM)

Bernie Meyerson is an IBM Fellow, vice president and chief technologist for IBM Systems and Technology (East Fishkill, N.Y.). His early experiments on silicon proved that assumptions about the material, held for more than three decades, were incorrect. Meyerson's resulting work in SiGe was groundbreaking, making IBM the leading SiGe chip provider for the communications industry, and helped form alliances with such giants as ADI, Alcatel, Tektronix, Hughes Electronics, National Semiconductor, Northern Telecom, Harris Semiconductor/Intersil and many others. Meyerson has a Ph.D. in physics from New York's City College, more than 180 published papers and over 40 patents.

SI: You have referred to immersion lithography as the door to progress in chip manufacturing. What do you mean by this?

Meyerson: Immersion lithography has the inside track on improving lithographic features' resolution and manufacturability. When you talk about conventional litho systems with NA=0.85, the fundamental advantage of immersion over dry litho is a significantly improved depth of focus (DOF). Now that we're at the advanced stage of using eight to 10 levels of metallurgy in products, as you develop more topography over the various levels involved in building the chip, it becomes critical to have a system capable of dealing with added topography that leads to DOF issues.

With extraordinarily large designs (it's not uncommon for people working at 90 or 65 nm to build chips on the order of 300 or 400 mm²), you also need the capability to deal with the very significant topographies that will develop across such large areas. By definition, immersion lithography and its DOF advantages has the inside track on resolving those issues. Beyond this, the 157 nm challenge is that the supporting infrastructure simply isn't mature enough for it to be viable at this time.

SI: You aren't writing it off?

Meyerson: You never write off a given technological concept. Nevertheless, there are significant challenges in the utilization of such short wavelengths, in terms of materials required to support operation at that particular frequency. We've seen a rapid increase in the search for alternatives to 157, even though some of them are equally as speculative at this time — EUV, for instance.

SI: So then delayed, not written off?

Meyerson: Immersion was rolled out with significant early successes. We were able to take an immersion system and produce the first commercial microprocessor using the technique. We printed the critical levels using immersion litho at the Albany center, using tools supplied by ASML. The ability to rapidly demonstrate a first-of-kind is what gives something like immersion lithography considerable credibility, pointing us in that direction. If you were to ask what will follow it, I'd say that it's still an open question.

SI: According to you, classical scaling of silicon technology died somewhere around the 130 to 90 nm node, and power consumption has hit a wall. This requires all sorts of new things, from materials to finFETs. How do you see the situation?

Meyerson: It is important to understand what one refers to when talking about classical scaling, and the fact that it's no longer viable. Regrettably, people mistake classical scaling as being directly related to Moore's Law, but it really has a loose relationship. Moore's Law, a stroke of brilliance, states that generation upon generation, you can expect an approximate doubling of the density of chip elements on a timescale of about 12-18 months. That, however, is not classical scaling. If you follow Moore's Law without classical scaling, at this point in time, a chip's power density would be in the tens of millions of Watts per square centimeter. The critical technical issue in shrinking technology is the maintenance of constant power density by following classical scaling.

Constant power density is achieved through the laws of classical scaling, where, if you think about it, what Moore's Law refers to is the area of a particular device element, and the rate at which that area shrinks. However, that is only X and Y — the area. Classical scaling requires that some 20 or more aspects of that device, beyond just X and Y, be shrunk to achieve the power density required to successfully move from generation to generation. What some in the industry have missed is that what had been lost was the ability to strictly adhere to the laws of classical scaling. You can always make a chip smaller, but if you also want to prevent a thermal runaway, you must follow the laws of scaling or find other innovations to achieve a smaller device that still works appropriately.

SI: When did this changeover take place?

Meyerson: The changeover, after which you could no longer properly scale all the required device elements, occurred between the 130 and 90 nm node. Gate oxide thickness is an example. The gate's oxide thickness didn't scale as it would have been expected between those nodes. In point of fact, gate oxide scaling has terminated. We've had various generations successively violating the laws of scaling, where, instead of the oxide getting thinner from generation to generation, it remains at a roughly constant dimension. That scaling failure led the industry to do other things in the process of making these devices, which has led to some of today's thermal issues. People have inappropriately held the operating voltage (V_dd) higher than scaling dictates, to compensate for the performance loss that results from the inability to further scale oxide thickness; however, this costs dearly in terms of overall leakage currents in the device, as well as the operating power. The breakage that is seen in processors came about because of a failure to recognize that, although Moore's Law continued, the glue that connected it to the ability to successfully access the next generation — classical scaling — had been lost. There is no question that we can continue to reduce the size of each device element, which is the continuance of Moore's Law. That isn't relevant to whether or not the next generation will be successful. We must find new materials through innovation to compensate for the fact that classical scaling, things working better because they got smaller, is no longer applicable.

SI: Is that why you believe that future performance lies in chip- and system-level innovation rather than shrinks?

Meyerson: Certainly the performance of future systems will be determined by the innovations one brings to the table. Now, shrinks will have the opposite of the intended effect. If you were foolish enough to do a complete normal "shrink," say between 90 and 65 nm or at 45 nm, and you did this blindly, continuing to reduce oxide dimensions from 10 to 5 Å, the chip would go into thermal meltdown. With a 5 Å oxide, leakage currents just through the gate alone would cause the transistor to immolate. It isn't that you cannot make features smaller — you can. You will still drive cost by shrinking the chip, but you will need tremendous innovations in materials, processes and structures to ensure that you still adhere to the required constancy of power density in the resultant entity.

SI: Computer power and capability have tended to set the semiconductor industry's course. Now that Intel has gone from single processor to on-chip multiprocessing, and we're withdrawing from the megahertz arms race, how do you see the future of computing devices between the extremes of a Power 5 and Blue Gene architecture if, as you say, clock speed has become irrelevant?

Meyerson: Around 1996, we considered the future of microprocessors and concluded that if we followed the traditional megahertz race — outdistancing everyone else by running the clock faster — eventually we'd hit a power wall. We therefore took a different path. In 2001, we shipped our first Power 4 machine, which used multicore processors. This dual-core design chip (two processors on a chip) got significant additional performance by being able to run both cores simultaneously. However, the clock frequency did not have to run as hard for the system to get very significant performance enhancements. That strategy, which is just now becoming pervasive in the industry, will become the rule, but will be taken to the next level.

In 2001, having already moved to multicore chips, the next logical step — and here things will become interesting — was making more efficient use of the assets within a system that has an abundance of processor cores, memory, network and storage assets. You can put so much on a chip today that within a relatively short span of time, even in the desktop world, you will see systems that can use architectural tricks that until recently were only found in the largest high-end servers. A couple of years ago, I coined a term that is becoming widely used: "holistic design." This is design where you consider all the elements, right from the microprocessor and semiconductor that supports it, all the way to the operating system, to optimize the user's IP experience; you micro-architect the entire system.

SI: So frequency is irrelevant?

Meyerson: In front of a terminal you don't see frequency, you see the output of a job and just hope it gets there sooner than otherwise.

SI: What about software?

Meyerson: Certainly when you have multiple cores available, you need software that can take advantage of them. This is a major change, because to leverage multiprocessing, you need software that supports multitasking and parallel processing. Another thing you must achieve is an optimization of how each individual core, or fractions of an individual core on a chip, is used. The capabilities against most workloads of even a single core are astonishing. Most workloads arriving at a core use only an infinitesimal fraction of that core's capability, but tie up the entire core. However, if the cores are multithreaded so that each one has two threads running through it, you can minimize the waste by having a fairly trivial calculation run through one thread on one core.

However, recent cores are massively powerful, and even tying up one thread for a computation can be hugely wasteful. For years the big servers have done something called "virtualization," where you take all the system's assets and virtualize them as individual proxies in software. These proxies are small instantiations of the system's capability — whether it be computing capability, storage, network or memory — and those capabilities are represented by a series of software proxies for each minimum unit of capability. This enables chips capabilities to be divided so that one thread, half a chip's power, can be further subdivided into tenths. Thus, when you represent a dual-threaded core, there are 20 proxies — 10 representations of each of the two threads in that core. Each proxy can now be assigned to a computing task, in which a supervisory program looks at the incoming workload and assigns to it the minimum computing power needed: a proxy representing one-twentieth of a core's capability, one proxy for memory, one for bandwidth, another for storage, and it assembles what amounts to a virtual system. This system then runs the computation using this minimal amount of system assets and energy, and drops the proxies back into a reserve when finished — these capabilities to be reused later for other purposes. We are fully approaching autonomic computing — a years-long goal. This is how the human body deals with the various inputs to it: It is self-healing, self-optimizing, self-realizing (but that's an entirely different issue). The key point is that the system is highly adaptive to its workload, and can enormously optimize the use of its assets. This is a very different model than today's, where all but the most sophisticated systems sit there doing nothing most of the time, and when they do work, they use a hard-coded scheme by which to operate.

SI: You have stated that basic technology no longer drives performance at the level that it once did, and argue for more open architectures. What would you like to see?

Meyerson: That's not quite true. What I said was that the method many in the industry used to drive performance — a simplistic reduction in size of devices — is no longer viable. As a consequence, we use innovation, as opposed to a simple shrink, to achieve the gains that we expected from shrinks in the past. The difference is that having to innovate leads to a fundamental and seminal shift in how the industry conducts itself. Some have made significant investments in innovation and will do well in that environment. Others who haven't invested in innovation will struggle, because they've been counting on the ability to gain performance through simple device shrinkage, which is no longer a viable alternative.

SI: How do you see the industry's progression toward true nanotechnology — self-assembly and the rest?

Meyerson: There are already situations where self-assembly and other techniques that involve nanoscale structuring are of immense value. You must rely on these, because the dimensions at which we're working are so far below those we've worked with before that we need to come up with other means for certain types of local assembly. For example, relatively early in our program we invested in SiCOH-based¹ low-k dielectric, a back-end-of-line insulator, along the way inventing the concept of using porogens. Porogens, when mixed with the basic material that ultimately forms low-k dielectrics that we use, segregate themselves in a very orderly and systematic manner out of the SiCOH matrix, forming small, extraordinarily reproducible nanoassemblies of tight dimensions. The unique chemical composition of these nodules enables them to be selectively removed from the matrix. You can use a radiation source, whether it be thermal, light or e-beam, and selectively break down the bonds only in these nanoscopic regions that have been formed through self-assembly, and have these materials diffuse out through the matrix, leaving a dielectric "Swiss cheese." As a result, you get an insulator with a dielectric constant significantly lower than the material had in bulk.

SI: Past the 45 nm node, how would you describe the problems facing the metrology and inspection equipment providers?

Meyerson: (Smiling) Rather small. All kidding aside, they are small problems. Unfortunately, in size, small problems are inversely proportionate to the difficulty of solving them. The issue is this: Inspection methodology can still involve the use of light, but you're getting to dimensions where that sort of imaging is insufficient. Thus, although you can inspect for gross features, gross particulate matter and such, at really small feature sizes, many of the inspection techniques are energetic — X-ray-based, e-beam-based, and the classic SEM/TEM — and you must become more creative to do the metrology. There's no shortage of techniques capable of taking you right to the atomic or subatomic scale, like AFM. The question is whether you can work them at a sufficiently high bandwidth to make them usable in the manufacturing environment, and make them sufficiently robust to survive the rigors of the thousand-wafer marathon. We're at the point where, when you're doing metrology on something like a gate oxide, you are looking at something composed of five or six atoms — layers in the range of 10-12 Å thick. The inversion thickness may be up around 18-24 Å, but the actual layer that constitutes your gate's physical entity could be at the level of a handful of atoms. We're dealing effectively with these challenges, and I see a successful pathway to working at these dimensions.

SI: Do you see design for test (DFT) becoming crucial?

Meyerson: Yes, for several reasons. The complexity of what we're building forces you to become increasingly aware of how challenging it'll be to actually test all aspects of a system's function. The densities that we're achieving are so extraordinary that, unless you put a system on a chip, it makes no sense to move to the aggressive lithographies. Having gone there, you then need to build in very clever adaptations of BIST (built-in self-test), such that you can be successful in demonstrating the ability to extract, as early as possible in the process, the success or failure of what it is you are attempting to build, so as to address the issue before going all the way through module testing to make the discovery. There will be a push toward making all these discoveries as early as possible in the cycle to reduce development costs and enhance time to market.

SI: What would you say is the biggest hurdle we're facing?

Meyerson: I have a reasonable level of confidence in what we're doing in virtually all of the manufacturing methods required to achieve the next several generations. The one area that I'd like to devote more resources to is fundamental work on materials. If you look at the complexity of introducing a fundamentally new material that will flow through all of our technologies over future generations, you want to be absolutely dead certain of the selection's viability. If we're going to replace the very heart of the device at some point — something like the gate dielectric — with high-k material, you want to ensure that you have previously devoted sufficient resources to avoid yield issues or finding out six months after the product leaves the plant that there are reliability issues. These cannot be discoveries. We must ensure that there is a viable new material roadmap for the future.