Chip Heat Removal With Microfluidic Backside Cooling

Anyone was has ever actually tried to use a laptop computer on one's lap knows that chips can generate an incredible amount of heat. One of the major challenges facing the semiconductor industry is how to remove heat from the chip, the board and the system.
 
Today, microprocessors are primarily packaged with a flip-chip approach, and the primary mode of heat removal is from the back surface of the silicon, often through a heat sink/spreader. The heat spreader is integrated with the back of the die using thermally conductive gels or epoxies.

By 2018, however, high-performance chips could produce a power density of 100 W/cm², according to the International Technology Roadmap for Semiconductors (ITRS). There is no manufacturable solution to remove such a high heat flux with conventional IC packaging technologies.

An interesting alternative, to be presented at the International Interconnect Technology Conference (IITC), to be held June 6-8 at the Hyatt Regency San Francisco Airport Hotel in Burlingame, is to remove heat by piping a coolant through microfluidic channels and heat pipes formed at the wafer level as part of wafer-level packaging interconnects. The approach, developed by researchers at the Georgia Institute of Technology, is compatible with CMOS and flip-chip technology, and it is compact and simple.

The Georgia Tech process begins following back-end-of-line (BEOL) fabrication of the interconnect system for chips on a wafer, prior to dicing the wafer into individual chips. Deep trenches are etched into the wafer backside and filled with a sacrificial polymer, which is then overcoated with a porous material (Figure ).

The illustration on the top shows the process sequence. The left photo shows a cross-section of an enclosed microfluidic channel, while the right photo shows through-silicon holes, used as inlets/outlets and aligned with the microchannels. The researchers concluded it should be possible to remove a heat flux of 100 W/cm2 with a pressure drop of <2 atmospheres. (Source: Georgia Institute of Technology)

The sacrificial polymer decomposes when the wafer is heated, leaving enclosed microchannels. A second overcoat is applied for enhanced mechanical strength and sealing. This overcoat may be a spin-on polymer layer, a high-quality SiO₂ thin film, or an electroplated metal sheet. The wafer is then bumped with a standard C4 process.

Through-chip holes and polymer "pipes" are used as inlets and outlets, formed by a thick layer of photo-imageable polymer on the front side of the wafer. The polymer pipes should be aligned with the inlet/outlet holes, then the passivation layer inside the pipes are etched to allow fluidic circulation.

After cleaning and drying, the wafer is ready for dicing. The resulting flip-chip can be mounted onto a liquid-cooled PWB substrate, which is equipped with embedded microfluidic channels and powered by integrated or external pumps for liquid circulation. Conventional underfill may be used to achieve a hermetic seal.

The team investigated two different channel-array designs, with multiple inlet/outlet configurations, to determine pressure drop across the cooling system and assess heat removal capability. The first design has 51 parallel channels and every three channels share a pair of inlet/outlet holes. In the second design, the channels are in a serpentine shape to achieve a more uniform temperature gradient.

Since the overall heat exchange area is identical for the two designs, their heat removal capability is the same for a given overall flow rate of any cooling liquid. The researchers say, to remove a heat flux of 100 W/cm² with DI water, the minimum overall flow rate of 0.4 cc/sec is required for a temperature difference of 60ºC between the inlets and outlets. They concluded it should be possible to remove a heat flux of 100 W/cm² with a pressure drop of <2 atmospheres.