Three-Dimensional ICs Solve the Interconnect Paradox

Interconnects are the focus of many chip design and fabrication challenges. They will eventually halt the crowding of transistors that has been key in making Moore's Law hold true. Transistors will soon have to be spaced significantly far apart to match an on-chip interconnect system that can handle their speed. When this happens, performance enhancements will have much more to do with the efficiency and creativity of architectures than raw transistor speeds.
 
Current approaches
 
For leading-edge ICs, the performance limitation comes from the longer, corner-to-corner global interconnects found in the upper wiring layers. Even with copper wiring and low-k dielectrics, some tricks are needed to keep the RC time constants of these global traces down. For example, making the wire layers as thick as possible maximizes each layer's volume. It also helps to make critical traces a little fatter where needed (Fig. 1 ).¹ X Architecture, promoted by the X Initiative, is providing needed help. The addition of 45° angles opens up some design space that can be used to minimize global interconnect lengths (see "X Architecture Becomes Mainstream ," Semiconductor International, April 2005). Intrachip networking is an approach for handling complex designs that might also tackle interconnect limitations. Sonics (Mountain View, Calif.) commercially introduced a socket protocol, which is now administered by the Open Core Protocol International Partnership (OCP-IP, Portland, Ore.), for the purpose of improving time-to-market for complex designs. Intrachip networking has also been proposed as a way of keeping wires busy, so that fewer might be needed.^2,3 In addition, high-speed signaling techniques can make global wires more efficient.⁴

After using all available approaches, a designer may still have to add another layer. This adds cost, but there are other reasons to avoid the use of additional layers. At some point, there will be a practical limit to the number of interconnect layers that an IC can have. Delamination becomes more likely as layers are added. Mechanical stability, which may already be low from the use of low-k materials, decreases as more layers are added.

With a practical limit on the number of interconnect layers, and a limit on how tightly the global interconnects can be packed, the global interconnects will soon force the die area to be significantly larger than the transistors would require (Fig. 2 ). The average spacing of all the wiring and transistors underneath will be affected.

1. This 130 nm technology, six-layer copper metallization example shows some of the tweaks used to optimize interconnect performance: high aspect ratios and fattening of critical traces. (Source: Intel)

2. When manufacturing and reliability concerns impose a practical limit on the number of metal layers, die sizes will increase to accommodate the global interconnects, and the average spacing between transistors will increase as a result.

To some extent, average transistor spacing in leading-edge ICs is already determined by the interconnect structure. Unfortunately, average transistor spacing will soon become so large that the number of die per wafer will decrease, eliminating the space-saving advantage of smaller feature sizes altogether.

3-D ICs

3. 3-D ICs are characterized by through-die interconnections, as shown in this cross-sectional view. (Source: Tezzaron Semiconductor)

Various forms of 3-D interconnection have been investigated for achieving a variety of goals. 3-D ICs, characterized by through-the-die vias (Fig. 3 ),⁵ promise to combat the interconnect paradox. There has been a large amount of university and industrial research on the subject over the years, and there have been two recent conferences on the subject. Companies currently offering 3-D IC technology commercially include Tru-Si Technologies (Sunnyvale, Calif.), Ziptronix (Research Triangle Park, N.C.) and Tezzaron Semiconductor (Naperville, Ill.).

3-D IC technology involves the bonding of finished die or wafers to each other. Good die from one wafer are picked and placed on the good die of an unsingulated wafer in the die-on-wafer approach. The wafer-on-wafer approach, in which wafers are bonded directly to each other, promises the highest manufacturing throughput, but it can also have the highest risk, depending on the attachment method.

Generally speaking, most who have examined the 3-D IC idea seem to think it has great potential. The one widely held issue against 3-D ICs, however, is that silicon surface area, enough for many transistors, is sacrificed for each through-via. This is only an issue, though, if transistors are densely packed. As discussed above, optimized designs in future generations will have "wasted space" caused by interconnect limitations.

Since this "waste" will be determined by the global interconnects, not the transistors or the local interconnects, the average transistor spacing will increase, but the local spacing can vary. It is conceivable that transistors and lower-level interconnects could be grouped into tightly spaced clusters to make room for interconnect vias, while sacrificing little, if any, additional space (Fig. 4 ). There are many variables to account for in this type of scheme, such as the number of intermediate layers, but it is still a scheme that warrants investigation.

4. Since global interconnects will determine the average transistor spacing, not the local spacing, it is possible to make room for interconnect vias with little effect on the die size.

Since upcoming designs will be interconnect-constrained, using the space between transistors for interconnects should be viewed as an opportunity to optimize the design, rather than a way to minimize wasted space.

Wafer-on-wafer integration promises the highest throughput, but its IC yield can be very small. For example, a stack of four wafers, each with a die yield of 90%, can give an IC yield as low as 66%. It would be unfair to compare the 90% yield in this example with the 66% yield, though, because they are yields for different things. The example depicted in Figure 5 makes this clear. One way of implementing the given IC is a single 20 mm square die. The other way is to make a stack of four die that are 10 mm squares. The examples in Figure 5 show representative results for manufacturing the IC on 200 mm wafers using a process that has five killer defects per wafer. If the same number of wafers holds the same number of ICs, and the same number of ICs is lost, then the IC yields are approximately the same. In either case, the yield may be unacceptably low, but the yield for the 3-D IC is no worse than the single-chip IC.

5. These two implementations of a 400 mm2 system on 200 mm wafers give approximately the same number of systems for the same amount of silicon. Even with the effective killing of good die (cross outs) by attachment to dead die (black outs), the system yield is approximately the same.

Advancements in wafer-level testing may provide a solution. If dead die could be identified with wafer-level testing, then wafers with the same defect patterns could be matched with each other. This would minimize the effective killing of good die, and may allow the 3-D IC yield to approach the die yield.

Of course, this is not the only yield question. There will be yield reduction associated with the attachment process itself. Questions about attachment yield are difficult to answer at this time; there seems to be a trade-off between cost and yield when choosing a 3-D integration method.

The integration methods can be broken down into two general categories: via-first and via-last. For via-last methods, vias are made in the wafer after it is bonded to the stack. The attachment component of the overall yield can be rather high for these schemes. For via-first schemes, the vias can be made and filled as a part of the front-end wafer processing, or at any time before wafer bonding. This can be more efficient and cost-effective than via-last approaches. However, it carries all the yield risk of a blind via process, and the vias are made in the die.

Tezzaron Semiconductor is using a 3-D process primarily for adding memory to an IC. The company has developed a method for reducing the number of memory cells that go unused when a cell goes bad. This method was developed, in part, to minimize the negative effects of unmade contacts between wafers. Since upcoming designs are expected to use an increasing memory component, a method like this could be useful in any case.

One of the important questions related to 3-D ICs is heat removal, because more heat-generating transistors will be in a small volume. In applications where every layer in a 3-D IC has logic running at top speed, this is a concern. In applications where an IC's performance is limited by a single hot spot in a logic block, a 3-D implementation can actually help. The other parts of the IC can serve as part of the heat sink for the hot spot and enable higher overall IC performance. In any case, the die in a 3-D stack are usually very thin, and the thermal path for removing heat through them is short. Also, through-contacts can serve as thermal vias, aiding heat removal.

An increasing portion of the heat generated in ICs comes from the wiring, with the increasing overall capacitance being the culprit. There is work supporting the idea that the reduced wire lengths in a 3-D IC will reduce the amount of heat that needs to be dissipated.^6,7 Much of the concern about heat removal comes from existing experience making 3-D ICs by connecting the die on the edges, where the wire lengths were not reduced.

The most promising performance advantage that 3-D ICs enable is placing more transistors within a clock cycle of each other.⁸ In three dimensions, this floorplanning exercise is more complex, but the potential to improve IC performance is worth the added design effort.

The possible advantages of 3-D ICs are not limited to solving interconnect-imposed problems. They can also provide all the advantages of using systems in a package (SiPs).⁹ Making memory and logic on separate wafers with their own processes can be less expensive than integrating them on the same die,¹⁰ though some believe this would give less than optimal performance.¹¹ Similarly, components can be made on their most appropriate materials, and integrated later to optimize performance and cost.¹²

Some applications require a 3-D topology. For example, a high-speed imaging application might require detectors on one layer and the first stage of processing circuitry immediately below on another layer. This would increase the fill factor the detectors have in the array, and their analog signals could be sent directly to the processing circuitry beneath.

Another possibility is an adaptable component model. This approach has its risks. In a way, this approach is already being considered for single-die ICs, in the form of package intermediated interconnects.¹² For 3-D ICs, it could be useful to have component die with more than one possible use.

Also, it has been proposed that 3-D ICs could provide the answer to Rent's rule. Assuming a value of two-thirds for the Rent's rule exponent, and using a 2-D surface bounding a 3-D circuit rather than a 1-D boundary around a 2-D circuit, it is possible for the boundary to grow at the rate needed by the circuitry.¹³ Work has been done recently to update Rent's rule for 3-D circuits.¹⁴

3-D IC technology will be a necessary consideration for future generations of ICs, and the technology is becoming viable. It can also enable applications that have not yet been possible with IC technology.^8,15 As the interconnect-constrained aspect of IC design becomes more significant, the presence of empty space on the die will become an opportunity to optimize a design, rather than a waste to be dreaded.

The expanded design space for 3-D ICs will be much more complex than the design space for current ICs. Within this expanded design space lie solutions that can be more elegant than those available with single-chip approaches, and the opportunity to enable applications that have not yet been possible. This will be a shift in focus from transistor packing to optimizing the computational power per unit volume in an interconnect-constrained environment.

The added design complexity associated with 3-D ICs will be necessary as the industry continues into the interconnect-limited era, and the time to prepare for this added complexity is right now.