Intel Finalizes 130 nm, Unveils New Prototype
-- Semiconductor International, 1/1/2001
Intel Corp., in two recent announcements, has said that it has completed the development of its 130 nm-generation logic technology, while also demonstrating what it claims to be the world's smallest and fastest CMOS transistor with a gate length of 30 nm. The announcements were centered around presentations at last month's International Electron Devices Meeting (IEDM) in San Francisco.Intel said it would begin volume manufacturing of devices with 130 nm dimensions this year, including a new generation of high-performance microprocessors that may contain more than 100 million transistors and run at multi-gigahertz clock speeds. The Figure shows how Intel plans to ramp 130 nm device production over the next two years.
Already, the company has built functional SRAMs and microprocessors using 130 nm technology, which features 70 nm transistor gate width, 1.5 nm gate oxide thickness, copper interconnects and low-k dielectrics (fluorinated SiO2; k=3.6). Intel claims to be the first to complete development of the 130 nm-generation process technology and demonstrate manufacturing readiness with complex ICs.
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"Intel's 130 nm process incorporates an unusually large number of simultaneous technology advancements," Chou added. "We started working on these advancements several years ago. We believe that our 130 nm process will be the earliest to ramp into volume production and to deliver products with leading-edge performance, density and power efficiency."
At IEDM, Intel researchers also described how they were able to fabricate 30 nm gate length CMOS transistors using conventional transistor design methodologies. The company said the development could enable it, in the next five to 10 years, to build microprocessors containing more than 400 million transistors, running at 10 GHz and operating at less than 1 V.
The transistors, which had 1.0 ps NMOS and 1.7 ps PMOS gate delays — among the fastest ever reported — were fabricated using aggressively scaled junction, polysilicon gate electrodes, gate oxide and Ni silicides. To achieve the 30 nm gate dimensions, a standard two-mask phase-shift mask approach was used with a 248 nm exposure system. To control short-channel effects and achieve sufficiently low external resistance and overlap capacitance, retrograded wells, aggressively scaled source/drain and source/drain extensions, and thermal anneal temperatures below 1000°C were used. No halo implant was used in the process flow. To minimize poly depletion effect with scaled junctions, the polysilicon gate thickness was scaled to below 100 nm.
"This breakthrough will allow Intel to continue increasing the performance and reducing the cost of microprocessors well into the future," Chou said. "As our researchers venture into uncharted areas beyond the previously expected limits of silicon scaling, they find Moore's Law still intact.''
"Many experts thought it would be impossible to build CMOS transistors this small because of electrical leakage problems," noted Gerald Marcyk, director of Intel's Components Research Lab, Technology and Manufacturing Group. "Our research proves that these smaller transistors behave in the same way as today's devices and shows there are no fundamental barriers to producing these devices in high volume in the future. The most important thing about these 30 nm transistors is that they are simultaneously small and fast, and work at low voltage. Typically, you can achieve two of the three, but delivering on all facets is a significant accomplishment."
Chou added, "It's discoveries like these that make me excited about the future. It's one thing to achieve a great technological breakthrough. It's another to have one that is practical and will change everyone's lives. With Intel's 30 nm transistor, we have both." •
—Peter Singer
