Three-Dimensional Silicon Approaches Are Increasing
John Baliga, Associate Editor -- Semiconductor International, 1/1/2001
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The thin-chip integration scheme developed by the Fraunhofer Institute (Berlin) was reported in this column last month. That work was done as a proof of concept for making customizable chips, using the institute's wafer-level packaging technology. Announcements on related schemes and accomplishments have also come out recently.
IXYS (Santa Clara, Calif.) recently received a patent for putting small die with control circuitry onto larger power ICs. The reason for doing this is that the voltages on the power ICs are much larger than what is required for the control circuitry, and it is simply more efficient to separate the power and its control than to integrate them on one die. Attaching the control die directly on top of the power die, rather than connecting them through a substrate, saves space. The die are electrically connected with wirebonds.
The Research Triangle Institute (Research Triangle Park, N.C.) recently spun off a company, Ziptronix, providing intellectual property for bonding wafers to each other. Its technology starts with a host wafer, to which another wafer is bonded at room temperature. The bulk of the second wafer is removed, leaving only the active circuitry. Vias are etched into the back of the second wafer to provide through contacts, and the process is repeated to form a stack.
About a year ago, Tru-Si Technologies (Sunnyvale, Calif.) first presented its stacked wafer process, which was based on its through silicon contact technology. For Ziptronix's technology, the vias are formed after attachment, and for Tru-Si the vias are formed at the beginning of wafer processing.
These two approaches make it possible to combine multiple wafers of different technologies or different materials into one stack that can be handled as a regular wafer. The separation of different IC technologies — such as logic, memory and analog — onto different wafers is one advantage put forward for pursuing these approaches. Stacking is an alternative to integrating these diverging IC technologies on one wafer. Putting power circuitry directly in the stack is also a possibility, which may also soon become a necessity for leading-edge ICs.
All of these approaches require wafer thinning. Usually, the wafer to be thinned is bonded to the stack or to a carrier wafer. Fraunhofer's approach uses CMP as the final step, which can reduce thickness variation. Ziptronix's technology could use CMP, though details have not yet been released. For Tru-Si's technology, the etch process exposes the contacts.
At the same time, capability for thinning and handling individual wafers continues to progress. SEZ recently announced that it has produced an 80 µm thick 300 mm wafer. The wafer was first ground, then etched in SEZ's spin etch equipment. Both SEZ and Tru-Si have demonstrated tools for handling ultrathin wafers.
However, transporting ultrathin wafers may be somewhat complicated. Standard pods are designed for rigid wafers. But because the sag for an ultrathin wafer is highly sensitive to the exact thickness, automated loading and unloading of pods would be a challenge. Taped wafers can simply be stacked on each other and transported in canisters, though there may be challenges associated with removing only one at a time, or removing a specific wafer. The wafer-stacking technologies listed can be performed in ways that avoid the handling of ultrathin wafers, which may be the best approach.
As the need for more functionality in smaller spaces continues, these three-dimensional approaches appear more promising. For applications that require the integration of dissimilar technologies, multichip approaches will become more attractive than system-on-a-chip. Methods and the required tools for performing these 3-D methods are available, and it may not be long before one or more of them is employed. •
For additional information and assembly & packaging, go to www.semiconductor.net/assembly.
