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Deuterium: The Secret Ingredient for Gate Oxides?

Peter Singer, Editor-in-Chief -- Semiconductor International, 1/1/2001

The challenges of continued scaling to smaller device structures and thinner films is perhaps felt most strongly in the area of gate oxides. Thermally grown oxides, which are inherently of very high quality, continue to be the dominant material used. But in order to maximize the drive current between the source and the drain of the transistor, thermal oxides must be very thin. For example, in Intel's 30 nm gate length CMOS transistor announced at the International Electron Devices Meeting (IEDM) in December (see Industry Watch for details), the gate oxide measures 0.8 nm thick. That's only three atoms! The end result was an inversion capacitance (Cox) of 1.9 µF/cm2.

A major concern with such thin gate oxides is their reliability. Typically, the thinner the gate oxide, the higher the stress-induced leakage current (SILC), leakage that occurs in the low gate voltage region after high-field stressing. SILC degrades performance and raises power dissipation, and has long stood as a barrier to realizing thinner gate oxides and enhanced device performance.

Long term, the solution seems to be gate dielectrics with higher dielectric constants (high-k dielectrics). This enables a thicker gate dielectric to be used, while still maintaining a high inversion capacitance. At IEDM, several papers were presented on zirconium and hafnium oxides, as well as aluminum oxide and one on praseodymium oxide (where did I put my periodic table?).

Short term, the reliability of oxides may be improved by doping them with various materials. For example, rapid thermal oxidation (RTO) in various nitrogen-containing atmospheres have been extensively researched, but with limited success.

Now, researchers at Toshiba Corp. (Yokohama, Japan) may have come up with the secret ingredient for optimizing gate oxide reliability. By adding deuterium through a process called deuterium pyrogenic oxidation, they have been able to achieve a significant reduction in SILC. While previous studies had confirmed the effectiveness of deuterium annealing in reducing interface-defect generation at the gate oxide-silicon substrate interface, Toshiba advanced the process to the level of suppressing SILC — and cut it by an amazing 30%.

The new process burns deuterium in ambient oxygen during the gate oxidation process, introducing deuterium atoms into the gate oxide as growing SiO2 film. Tests confirm that the process achieves more stable chemical bonding of deuterium atoms than the annealing process. SILC suppression was rendered even more effective by replacing SiH4 gas with SiD4 gas during polycrystalline silicon deposition of the gate electrode. The number of deuterium atoms in the SiO2 film after polycrystalline silicon deposition by SiD4 gas was 10 times larger than achieved with deuterium oxidation alone.

The chief value of Toshiba's new oxidation process is its strong potential as a real-world solution compatible with the conventional oxidation process. Suppression of SILC can be achieved simply by changing from hydrogen gas, widely used for the gate oxidation process, to deuterium gas. The equipment required is essentially the same as that currently used in the fabrication process. This new process can also be applied to realize higher reliability in thin-tunnel oxides for nonvolatile memories.

The devices used in the work were n-channel MOSFETs and MOS capacitors fabricated on Si(100) substrates. Gate oxides were grown in a pyrogenic ambient using hydrogen or deuterium at 850°C. MOSFETs and a part of the MOS capacitors were annealed in hydrogen or deuterium ambient at 450°C.

The researchers said that a similar approach, in which the oxide is annealed in deuterium, shows no improvement in gate oxide reliability. In the case of a deuterium-annealed oxide, deuterium atoms exist mainly at the SiO2 interface, while they are contained in the entire SiO2 film in the case of deuterium-pyrogenic oxide.

Details of the new gate oxide fabrication method of work, which was partly performed under the management of ASET (Association of Super-Advanced Electronics Technologies) in a MITI (Ministry of International Trade and Industry) R&D program supported by NEDO (New Energy and Industrial Technology Development Organization), were presented at the recent IEDM Conference. •

For additional information on wafer processing, go to www.semiconductor.net/wafer
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